Mar 2024 – May 2026 · 2 yrs 2 mos

Sep 2021 – Mar 2024 · 2 yrs 6 mos

Jan 2020 – Sep 2021 · 1 yr 8 mos · San Jose, CA

Jan 2019 – Jan 2020 · 1 yr · Santa Clara, CA

• Worked on the Vector Core architecture and design, based in the RISC-V architecture ISA, and V extension.

Sep 2017 – Dec 2018 · 1 yr 3 mos · San Francisco Bay Area

• I work on Research and Development of systems architecture for new memory technologies, like 3D Xpoint (3DX).

Jan 2014 – Sep 2017 · 3 yrs 8 mos · San Francisco Bay Area

• Research in Storage Architecture and Non-Volatile Memories
• Research in Storage Architecture and Non-Volatile Memories;
• We investigate high-performance interfaces like GenZ, OpenCAPI, RapidIO for storage systems;
• RISC-V applications for SoC;
• New Memory bank architectures;
• Microprocessors Architectures, specifically working in the memory hierarchy design;
• Microelectronics techniques that can be leveraged in storage;
• Gen-Z;
• OpenCAPI;
• CAPI;
• RapidIO;

Jan 2014 – Sep 2017 · 3 yrs 8 mos · San Francisco Bay Area

• Research in Storage Architecture and Non-Volatile Memories;
• We investigate high-performance interfaces like GenZ, OpenCAPI, RapidIO for storage systems;
• RISC-V applications for SoC;
• New Memory bank architectures;
• Microprocessors Architectures, specifically working in the memory hierarchy design;
• Microelectronics techniques that can be leveraged in storage;
• Gen-Z;
• OpenCAPI;
• CAPI;
• RapidIO;

Jan 2010 – Nov 2013 · 3 yrs 10 mos · Greater Montpellier Metropolitan Area

• Compare SRAM versus MRAM on CACHE L1 and L2 (power, performance, area);
• MRAM characterization;
• MRAM research;
• Analyses of Power, Area on CMOS circuit;
• MRAM memory Cells test;
• MRAM Mitigation mechanism for memory banks to replace SRAM banks on L1;
• Explore different CACHE memory parameters (L1 and L2);
• Synthesize and P&R: PowerPC, OpenSPARC, Leon3, OpenRISC for 45nm NanGate;
• Synthesize and P&R: OpenSPARC, Leon3, OpenRISC for FPGA;
• ECC for FPGA 65nm ST and below to improve reliability;
• toolchains for SPARC;
• Gem5;
• CACTI;
• NVSim;
• DDR power model;
• Create an integrated power analyses methodology combining Gem5+CACTI+NVSim+DDR;
• write papers;
• review papers;
• book chapter;
• Lectured at UM2 from August to December 2011;
• projects ANR MARS, ANR CILOMAG, EU Modern, ANR SPINTEC.

Jun 2007 – Jul 2008 · 1 yr 1 mo

• Project of AED financed by Instramed and FINEP;
• Research the technology for a semi-automated AED;
• Development of an RTOS that embeds the pattern recognition algorithm tested in an off-the-shelf microprocessor and FPGAs;
• SoC design;
• Replacement of a Welch Alley Oximetry module by the Oridion module in the existing multi-parametric device of the company.

Jan 2005 – Oct 2007 · 2 yrs 9 mos · Sao Leopoldo, RS, Brazil

• Lectured Programming Languages: C, C++ and Java.
• Lectured System Development based on Java,
• Lectured Object-Orientation;
• Lectured UML;
• Lectured Introduction to Networks;
• Lectured Operating systems.

Jan 2005 – Jan 2006 · 1 yr

• Research and Development of ECC IC implementations;
• Reed-Solomon for the SbTVD (Brazilian Digital Television System);
• AEB (Brazilian Aerospace Agency) for the TM/TC module according with the CCSDS standards;
• BCH for SbTVD;
• Designed a new ECC code (MDECC).

Jan 2004 – Jan 2006 · 2 yrs · Porto Alegre, RS, Brazil

• Research and development of Semiconductors for Error Correcting Codes and fault tolerant systems to a joint project between INPE and AEB (National Institute of Spacial research and Brazilian Aerospace Agency);
• contributed to the UNIESPAÇO program, in association with INPE, developing a telecommand / telemetry system for AEB (Brazilian Aerospace Agency) targeting reconfigurable devices, in conformity with CCSDS regulations;
• Research and development of Semiconductors for Error Correcting Codes and fault tolerant systems to a joint project between INPE and AEB (National Institute of Spacial research and Brazilian Aerospace Agency).

Jan 2003 – Jan 2005 · 2 yrs · Greater Porto Alegre

• detail the complete specification from scratch of a router device;
• components selection;
• the entire set of softwares(application, cross-compilers, libc, OS, kernel, bootloader);
• OS and applications;
• the development of the bootloader and toolchains we used for the PowerPC architecture processor;
• OS device drivers;
• The chipset for interconnection of the VoIP (FxS FxO) additional interfaces for our system (RTL design in-house);
• Voice Codecs;
• VoIP Jitter Buffer;
• Wan chipset design;
• uBoot bootloader for the customized PCB boards;
• SDRAM dynamic memory identification during boot (uBoot);
• Linux for embedded PowerPC;
• Toolchains for PowerPC;
• RTL coding of a chipset to interconnect FxS FxO interfaces to the main PPC;
• Snort Firewall device;
• Embedded command-line UI into the routers;
• Wan Linux device driver;
• GSM device driver;
• GSM channel mux;
• Embedded VoIP Asterisk on PowerPC
• Voice Codecs tuning (G729A/B, G711, G721, aLaw, uLaw, PCM);
• Flash NOR AMD replacement by Micron Flash, changes in bootloaders and OS Kernel
• Routing tools;
• Design of Wireless router using Siemens GSM module.

Jan 2001 – Sep 2001 · 8 mos

• Parallel systems, High Performance Computing
• CPAD lab

Aug 1999 – Jan 2001 · 1 yr 5 mos

• Embedded systems
• GPPSDI lab

Jan 2001 – Jan 2003 · 2 yrs

• - Telecommunications Research and development