Vinayak Ray

Software Engineer

Bengaluru, Karnataka, India17 yrs 7 mos experience

Highly Stable

Key Highlights

15 years of verification experience across multiple domains.
Expert in managing complex regression and triaging failures.
Proven track record in optimizing verification cycles.

Stackforce AI infers this person is a highly skilled engineer in semiconductor verification and validation.

Contact

Skills

Core Skills

RiscvDebuggingFunctional VerificationLow Power VerificationX86Soc VerificationPre And Post Silicon Verification

Other Skills

Joint Test Action Group (JTAG)Unified Power Format (UPF)SystemVerilogC++Universal Verification Methodology (UVM)ARMCPUARM Cortex-MAMBAPerlVerilogProcessorsSoCHardware ArchitectureSimulations

About

15 years of verification experience in multiple domains and roles. LPDDR3/4/5 based PHY, ARM based SOC,X86 CPU pipeline . My key skills include Functional verification, Gate Level simulation (GLS,SDF), Low power verification(UPF) and support to post silicon debug team. I try to challenge myself as an engineer, taking up complex roles outside my comfort zone. Moving over to X86 processor verification with C++ based testbench was one of them. Currently I am working on managing regression of RISCV cores. The main challenges have been triaging failures which are in thousands. I have used statistical methods to create triaging mechanisms. It gives good results but needs fine tuning. I have successfully executed several initiatives to refactor codes that simplify logic and reduce simulation time and make components scalable. My current interests are optimising verification cycle and catching more of silicon issues in pre-silicon verification.

Experience

17 yrs 7 mos

Total Experience

2 yrs 7 mos

Average Tenure

1 yr 8 mos

Current Experience

Tenstorrent

Senior Staff Engineer

Oct 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · Hybrid

Worked on JTAG tests creating script which abstracted the scan chain length and ID programming.
Currently working on RISCV core debug and regression management where the responsibility entails maintenance of pass-rate of curation tests and smoke and making sure the regression go through without any major issues of infra. Enabling features based on metrics and ownership delegation based on failures.
Regression handling is matter of handling large numbers, around 100k tests each week. One of my eforts has been to handle such complexity through statistical means rather than conventional. Based on such effort created regression triaging script using K means clustering. The script can parse logs and find out the unique flavours of underlying root-cause. Finetuning is still work in progress.

RiscvJoint Test Action Group (JTAG)Debugging

Qualcomm

Senior Staff Engineer

Dec 2022 – Oct 2024 · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

Leading a small team to validate the PHY supporting high speed low power LPDDR protocols. The team is exposed to the most advanced technologies and innovation instrumental in delivering class leading power, performance and area optimized products in mobile and compute.

Unified Power Format (UPF)SystemVerilogC++Universal Verification Methodology (UVM)ARMX86+3

Amd

MTS

Mar 2019 – Nov 2022 · 3 yrs 8 mos · Bengaluru Area, India

X86 processor verification targeting decode pipeline. The design is responsible for decoding X86 instructions and converting them into micro-architectural instructions.
My responsibilities include testplan update, debug regression failure and coverage closure.

X86Debugging

Qualcomm

3 roles

Senior Lead Engineer

May 2017 – Mar 2019 · 1 yr 10 mos · Bengaluru Area, India

8 years of SOC Verification experience with 8 tapeouts from 28nm to 7nm technology nodes. Domain expertise in LPDDR3/4, pre and post silicon verification. Worked with Cortex A,R,M series processor with exposure to core register and assembly to C function mapping.
Key skills include netlist verification, timing simulation, constraint miss and design issues isolation, vector creation and silicon debug. Open to taking up challenges outside comfort zone.
Successfully executed several initiatives to cut simulation time and simplify debug. Future interests include mitigating post silicon issues through pre-silicon verification, reducing verification time with bigger designs.

ARM Cortex-MAMBASOC VerificationPre and Post Silicon Verification

Senior Engineer

Oct 2014 – Mar 2019 · 4 yrs 5 mos · Bengaluru Area, India

Project: Single channel LPDDR4 targeting
New packet based SOC architecture with dynamic bandwidth voting to control chip operation. Responsible for pre-silicon verification of data/ control path to DRAM. Executed low power verification(UPF) and debugged several isolation related issues.
Achievements: Debugged a showstopper issue, where cache tagram was getting corrupted during power collapse due to glitch.
Project: Chipset targeting server market
8 channel LPDDR4 with system cache. Challenges included maintaining coherency across multiple masters and L1/L2 cache of main processor.
Scope of verification included LPDDR4 access, per master cache partitioning, driver support for system level coherency check.
Achievements: Mentored new team members to ramp up on LPDDR4 and new SOC architecture. Debugged transaction ID mismatch in one of the NOCs (outside domain knowledge), which caused random transactions to be routed as different response ID.
Senior Engineer
Project: Mobile chipset (LPDDR3/4)
ARM based chipsets targeting mobile handsets, spanning across Gen 1,2.5 and 3 DDRPHY. Involved in 4 tape-outs, which included verification of LPDDR4 based memory controller and QSPI based controller
Achievements: Ported and verified QSPI at SOC-level. Had no previous exposure to this controller yet successfully executed in timebound manner.
Awarded Qualstar for coming up with initiative to replace LPDDR MC with slave memory. Reduced verification time
Debugged many critical timing/constraint related issue – Wrong routing of clock, incorrect ping-pong mux behavior, hold violation due to incorrect synthesis.

ARM Cortex-MLow Power Verification

Senior Lead Engineer

Oct 2014 – Mar 2019 · 4 yrs 5 mos · Bengaluru Area, India

ARM Cortex-MAMBA

Texas instruments

Senior Design Engineer

Mar 2012 – Sep 2014 · 2 yrs 6 mos · Bangalore

Programming languages and tools: C, ASM, NCSIM
Worked in a cross functional team for verifying ARM based automotive safety microcontrollers. Responsible for verification of sub-blocks from RTL to netlist. Verified netlist in all PVT corners. Delivered AC characterization vectors and debugged failure on silicon.
Achievements: Hacked existing design and replaced existing block with MMC- Achieved through event based TCL scripting only. Dumped ARM core register in log on failure. This reduced debug effort.
Onsite Experience: 1 month (2014.04 – 2014.05) for vector delivery and debug, Houston.

ARM Cortex-M

Amcc

Hardware Design Engineer

Aug 2009 – Feb 2012 · 2 yrs 6 mos

Programming languages and tools: C, SV, Questasim
Verification of boot from SATA, SDIO, I2C. Support for decryption(SHA128/256) during boot. Ported block level test to SOC level. Learnings spanned from decoding processor booting, TLB entries to understanding encryption algorithm.
Achievements: Integrated BCH-ECC model in verification flow to generate ECC values of boot code dynamically. Speed I2C fetch from EEPROM reducing verification time. Modified existing RTL generation script to generate header and macros for write read operations

ARM Cortex-MAMBAUniversal Verification Methodology (UVM)