Vinay K H

Software Engineer

Bengaluru, Karnataka, India13 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and semiconductor verification methodologies.
Proven track record in developing comprehensive verification environments.
Strong leadership in cross-functional technical collaborations.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in VLSI design and verification.

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Skills

Core Skills

Semiconductor EngineeringUniversal Verification Methodology (uvm)Verification Testplan DevelopmentProject ExecutionSerdesUvm VerificationSystem Verilog Assertion Based VerificationSystem Verilog Assertions

Other Skills

Formal VerificationSystem on a Chip (SoC)RTL VerificationAssertion Based VerificationTechnical Sync-upsGate-Level SimulationAPBAHBAXI Protocols12 bit ADCFunctional CovergroupsCoverage PointsPlanning Budgeting & ForecastingCoordinating SchedulesDebugging Code

About

Protocols : AMBA- APB ,AHB, AXI, I2C Mixed Signal:SerDes,ADC Methodologies : UVM HVLS: Verilog,System Verilog

Experience

13 yrs 1 mo

Total Experience

2 yrs 6 mos

Average Tenure

3 yrs 8 mos

Current Experience

Samsung electronics

Senior Staff Engineer

Oct 2022 – Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

Semiconductor EngineeringUniversal Verification Methodology (UVM)Formal VerificationSystem on a Chip (SoC)RTL VerificationAssertion Based Verification

Samsung semiconductor india r&d

Senior Staff Engineer

Oct 2022 – Present · 3 yrs 8 mos

Set up a complete verification environment including infrastructure bring-up, regressions. Developed a comprehensive verification testplan aligned with architecture and design requirements. Drove regular technical sync-ups with design/architecture teams for issue triage and progress tracking. Brought up the GLS (Gate-Level Simulation) testbench and enabled early timing and synthesis validation. Ensured on-time project execution and successful verification signoff with high quality.

Amd

Senior Design Engineer

Oct 2020 – Sep 2022 · 1 yr 11 mos · Bengaluru, Karnataka, India

Amd india pvt ltd

Senior Design Verification Engineer

Aug 2019 – Sep 2022 · 3 yrs 1 mo

Drove both functional verification and integration-level validation, ensuring full feature and corner-case coverage. Introduced formal verification techniques (connectivity, property checks) to accelerate DV signoff and reduce overall verification cycle time.

Alten calsoft labs

Senior Design Verification Engineer

Aug 2019 – Oct 2020 · 1 yr 2 mos · Bengaluru Area, India

Worked for AMD India : Infinity Fabric IP

Broadcom inc.

Design Verification Engineer

Jun 2012 – May 2016 · 3 yrs 11 mos · Bengaluru Area, India

Worked on SerDes , ARM's Core NIC 400 :APB,AHB,AXI Protocols
UVM Verification environment. System Verilog Assertions

Broadcom india pvt ltd

Design Verification Engineer

Jun 2012 – May 2016 · 3 yrs 11 mos

Developed SerDes Usage assertion plan and verified the same using system Verilog assertions(SVA). Developed the functional coverage points for the features. Debugging the failure cases.

Microchip technology

Verification Engineer

Jan 2011 – Jul 2012 · 1 yr 6 mos

Worked on PIC MicroControllers -12 bit ADC , System Verilog Assertion Based Verification

Microchip india pvt ltd

Design Verification Engineer

Jan 2011 – May 2012 · 1 yr 4 mos

Developed the Testplan for the ADC module to implement System Verilog Assertion and Coverage. Developed the SV Assertions for 12 bit pipelined ADC. Developed functional Covergroups and Coverpoints.

Whizchip solutions pvt. ltd

Student

Aug 2009 – Aug 2010 · 1 yr

MS Academic project 1 Year
Understanding of AMBA-APB Protocol and I2C Protocol
Developed the Wrapper for APB Master to communicate with I2C Slave, using Wishbone I2C master as a bridge
Developed the Verification plan
Developed testcases in Verilog HDL