H

Harsha Balan

Director of Engineering

Bengaluru, Karnataka, India28 yrs 2 mos experience

Key Highlights

  • Expert in VLSI design and functional verification.
  • Proven leadership in managing engineering teams.
  • Extensive experience in semiconductor industry projects.
Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong leadership in VLSI and verification.

Contact

Skills

Core Skills

LeadershipEthernetFunctional VerificationVlsiSpec-to-gdsVerification

Other Skills

RTL codingDVSynthesisDFTSTALTE5GInternet Protocol Suite (TCP/IP)IPv6SoCVerilogVeraVLSI designCommunication systems standards and protocolsPeople Management

About

Experienced Senior Manager with a demonstrated history of working in the semiconductors industry. Skilled in VLSI design, Communication systems standards and protocols, Functional Verification, Spec-to-GDS, and People Management. Strong professional with a Master of Engineering focused in Information Technology from Birla Institute of Technology and Science.

Experience

28 yrs 2 mos
Total Experience
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Average Tenure
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Current Experience

Qualcomm

2 roles

Director, Engineering

Promoted

Apr 2021Dec 2024 · 3 yrs 8 mos

Leadership

Engineer, Principal Manager

Jan 2019Mar 2021 · 2 yrs 2 mos

EthernetLeadership

Mediatek

Senior Manager

Mar 2015Jan 2019 · 3 yrs 10 mos · Bangalore

  • Connectivity Technology Development BU : Integration of connectivity IPs into Smartphone chips. Ramping up a new team for complete subsystem sign-off including RTL coding, DV, Synthesis, DFT,, STA and quality checks.
  • Wireless Communication Technology BU: Leading a functional verification team for LTE and 5G Modem technologies.
EthernetLeadershipFunctional VerificationVLSI

Lantiq communications (india) private limited

Principal Engineer

Nov 2009Mar 2015 · 5 yrs 4 mos · Bangalore

  • Executed DSL and home networking SoC development projects being responsible for all activities from specification to GDS as well as post silicon system bring-up.
EthernetLeadershipSpec-to-GDS

Infineon technologies

Staff Engineer/ Sr. Staff Engineer

Oct 2004Oct 2009 · 5 yrs · Bangalore

  • Developed standard compliant verification environments for very large and complex SoCs. Lead teams of engineers to implement multimillion gate designs for DSL applications.
Internet Protocol Suite (TCP/IP)IPv6Verification

Cisco systems

Hardware Engineer

May 2000Sep 2004 · 4 yrs 4 mos · Bangalore

  • Implemented Verilog and Vera based verification environments for various packet processing ASICs.
Internet Protocol Suite (TCP/IP)IPv6Verification

Cadence design systems

Lead Engineer

Jul 1996May 2000 · 3 yrs 10 mos · Noida, Uttar Pradesh, India

  • Tool flow validation for system design and simulation

Education

Birla Institute of Technology and Science, Pilani

ME — Software Systems

Jan 1995Jan 1996

National Institute of Technology Warangal

B. Tech — Electrons and Communication

Jan 1989Jan 1993

St. Joseph's college, Bangalore

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