Anand Saurabh — Software Engineer
I am a Result-driven professional holding Masters in Microelectronics & VLSI from IIT Kharagpur having 2 years of experience (Out of Total 3+ years) in RTL Design, Verilog, VHDL, Static Timing Analysis, Clock Domain Crossing methodologies and using VIVADO and Questasim for FPGA design and simulation.
Stackforce AI infers this person is a skilled RTL Design Engineer with expertise in VLSI and FPGA technologies.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 7 mos
Skills
- Verilog
- Static Timing Analysis
- Vhdl
- Radio Frequency (rf)
- Electronic Circuits
- Data Analysis
Career Highlights
- Masters in Microelectronics & VLSI from IIT Kharagpur
- Over 3 years of experience in RTL Design and FPGA
- Proficient in Verilog and VHDL for digital design
Work Experience
Samsung Semiconductor
RTL Design Engineer (2 yrs 1 mo)
AppEx Semiconductor Pvt Ltd
RTL design engineer (1 mo)
AMD
Silicon design Engineer 2 (1 yr 8 mos)
Avench Systems Pvt Ltd
RTL Design Engineer (4 mos)
Qualcomm
Associate Radio Frequency Engineer (1 yr 6 mos)
Abzooba Analytics (UST)
Software Engineer Intern (2 mos)
Education
Master of Technology - MTech at Indian Institute of Technology, Kharagpur
Bachelor of Technology - BTech at Indian Institute of Technology, Guwahati