Anil Deshpande — Director of Engineering

PROFESSIONAL SUMMARY ▸ Seasoned Engineering Director with 20+ years of end-to-end IP and SoC Design Verification leadership across advanced process nodes (28nm–2nm+). ▸ Currently working as Director at Samsung Semiconductor India's Foundry IP Development organization — a 50+ engineer Verification Centre of Excellence delivering silicon IP for Exynos SoCs and HPC/AI platforms for Samsung, Tesla, NVIDIA, Google, and Microsoft. ▸ Deep technical expertise in System Verilog/UVM,Funtional/performance, Formal Verification, Assertion-Based Verification (ABV), and accelerated/emulation-based methodologies. ▸ Proven at building world-class verification organizations, architecting zero-defect DV infrastructures, driving AI/ML-powered automation, and influencing global semiconductor standards. ▸ Track record of 9+ consecutive first-pass silicon successes in AP/Auto/HPC AI SoC's across Memory (HBM3/4, LPDDR5/6), High-Speed Interfaces (PCIe, UCIe, 224G Ethernet), and Security/Cryptography IP families. CORE TECHNICAL & LEADERSHIP COMPETENCIES ▸ Simulation / Emulation / FPGA Prototyping | Post-Silicon Validation | DFT & Scan Methodology | RTL Sign-Off ▸ System Verilog / UVM | Formal Verification (Jasper Gold, VC Formal) | Functional Coverage & CDC ▸ Memory Sub-Systems (HBM3/4/4e, LPDDR5/6) | High-Speed Interfaces (PCIe 4/5, UCIe-3D, 224G Ethernet, MIPI) | Security IP (AES, SHA, PQC) ▸ ARM (Cortex-A/M, Tegra) , RISC-V & x86 SoC Architecture | ISO 26262 / ASIL-D Functional Safety | AI/ML-Driven Verification Automation ▸ Engineering Organization Scaling | Cross-Site Program Management | EDA & VIP Ecosystem (Synopsys, Cadence, Mentor) | JEDEC / MIPI Standards ▸ Experince working on AI Deep Learning and Machine Learning Applications,AI Model Training/Inferencing.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on AI-driven methodologies.

Location: Bengaluru, Karnataka, India

Experience: 20 yrs 8 mos

Skills

Engineering Management
System Verification

Career Highlights

20+ years in IP and SoC Design Verification leadership.
Achieved 9+ consecutive first-pass silicon successes.
Expert in AI/ML-driven verification automation.

Work Experience

Samsung Semiconductor India Research

Director of Engineering (3 yrs 3 mos)

Associate Director (4 yrs 11 mos)

Senior Engineering Manager (2 yrs 1 mo)

NVIDIA

Sr.ASIC Engineer (3 yrs 11 mos)

AMD

Sr.Design Engineer (2 yrs 8 mos)

NXP Semiconductors

Hardware Design Engineer (2 yrs 5 mos)

Conexant

Design Engineer (1 yr 7 mos)

Avantel

Design Engineer (1 yr 5 mos)

Education

Computer Science at Stanford University

EGMP at Indian Institute of Management, Lucknow

B.Tech at Jawaharlal Nehru Technological University

Anil Deshpande

Director of Engineering

Bengaluru, Karnataka, India20 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

20+ years in IP and SoC Design Verification leadership.
Achieved 9+ consecutive first-pass silicon successes.
Expert in AI/ML-driven verification automation.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on AI-driven methodologies.

Contact

anildesh@gmail.com LinkedIn

Skills

Core Skills

Engineering ManagementSystem Verification

Other Skills

Artificial Intelligence (AI)Deep LearningMachine LearningSystem VerilogUVMFormal VerificationFunctional VerificationSecurity IPAI/MLVerification AutomationUCIe-3DPCIeAESSHA-2/3Post-Quantum Cryptography

About

Experience

20 yrs 8 mos

Total Experience

3 yrs 8 mos

Average Tenure

10 yrs 3 mos

Current Experience

Samsung semiconductor india research

3 roles

Director of Engineering

Promoted

Mar 2023 – Present · 3 yrs 3 mos

▸ Leading Samsung's India IP Design Verification Center of Excellence — responsible for Functional/Performance verification, formal verification, and silicon sign-off of Memory, High-Speed Interface, and Security IPs across nine generations of Exynos SoCs and HPC/AI foundry programs.
▸ Architected scalable, reusable System Verilog/UVM verification environments and Formal Verification (Jasper Gold) infrastructures across HBM3/4/4e/5, LPDDR4/4x/5/5x/6, UCIe-3D, PCIe 4/5, and Security Sub-Systems, enabling concurrent multi-program sign-off across 28nm–2nm nodes.
▸ Achieved 9+ consecutive first-pass silicon successes — including multiple World's First IP Productization — through rigorous DV closure methodology covering functional simulation, formal verification, CDC analysis, power-aware (UPF) verification.
▸ Drove AI/ML-based verification automation initiative: deployed ML-driven test prioritization, automated coverage convergence, and intelligent regression management
▸ Defined and executed verification strategy for High-Speed Interface IPs:
UCIe-3D, PCIe Gen4/5, 56G/224G Gigabit Ethernet, MIPI CSI/DSI/DCPHY/Unipro/MPHY — architecting protocol-compliant UVM VIP environments and Formal checkers for each interface family.
▸ Led Security & Cryptography IP Verification Center of Excellence:
Comprehensive DV coverage of AES, SHA-2/3, SM3/SM4, Post-Quantum Cryptography (PQC), PUF, TRNG, eMRAM, and Flash Controllers; delivered FIPS-compliant verification closure for foundry customers.
▸ Delivered ASIL-D compliant IP verification for automotive SoC programs under ISO 26262 — including Fault Injection testing, FMEDA integration, and safety mechanism verification; methodology adopted org-wide.
▸ Established emulation and FPGA prototyping infrastructure for SoC-level pre-silicon validation; enabled firmware bring-up 8 weeks ahead of tape-out on multiple programs, reducing post-silicon debug cycles by 35%.

Artificial Intelligence (AI)Deep LearningMachine LearningSystem VerilogUVMFormal Verification+4

Associate Director

Promoted

Mar 2018 – Feb 2023 · 4 yrs 11 mos

Senior Engineering Manager

Jan 2016 – Feb 2018 · 2 yrs 1 mo

Nvidia

Sr.ASIC Engineer

Feb 2012 – Jan 2016 · 3 yrs 11 mos · Bangalore,India

▸ Engineered world-class verification environments for NVIDIA GPU,CPU microarchitectures using UVM and constrained-random methodologies to accelerate coverage closure.
▸ Led complex RTL-to-silicon verification flows for GPU compute units and memory subsystems, driving regression scalability and first-silicon quality improvements.
▸ Developed robust verification IP and scoreboard frameworks for high-throughput GPU ,coherent fabric
▸ Having experience on many sub system unit level verification like clocks,fuses,RTC,LA, Power Management Controller
▸ Owned unit and sub-system DV for Tegra SoC IPs targeting automotive ADAS and AI inference — designed and verified cache coherence, memory controller, and power management subsystems using SV/UVM.
▸ Drove GPU subsystem verification closure (Kepler–Pascal architecture): coordinated multi-site DV teams on cache coherence, NoC interconnect, and power validation work streams; achieved zero post-silicon escapes.
▸ Applied ARM Cortex-A/M and x86 CPU architectural knowledge to define IP-level verification plans, guiding power/performance/area (PPA) trade-off decisions and DV prioritization strategies.
▸ Introduced constrained-random UVM environment enhancements that increased functional coverage closure rate by 30% and reduced regression runtime by 25% through intelligent test scheduling.
▸ Performed performance verification of GPU/SoC subsystems including NoC and memory
▸ Validated QoS, arbitration, and bandwidth efficiency
▸ Collaborated with architecture teams on PPA trade-offs

Amd

Sr.Design Engineer

Jun 2009 – Feb 2012 · 2 yrs 8 mos · Greater Hyderabad Area

▸ RDNA GPU DV: Verified shader pipelines, caches, and high-throughput datapaths using advanced C/C++,UVM, SVA, and coverage-driven methodologies.
▸ Game Console SoC DV: Verified next-gen PlayStation/Xbox SoC IPs with focus on coherency, interconnects, and high-performance multimedia blocks.
▸ Delivered high-quality test plans, coverage closure, and silicon-proven verification for multiple tape-outs.
▸ Worked with customer for developing Test Plan for Power Management .
▸ Verified x86 CPU cores, cache controllers, and power management subsystems for AMD's first Fusion APU; established low-power UPF-based verification flows adopted across multiple product lines.
▸ Developed reusable verification components for power management IPs; influenced product-level power specifications for Xbox and PlayStation platforms through early DV-driven PPA analysis.

Nxp semiconductors

Hardware Design Engineer

Jan 2007 – Jun 2009 · 2 yrs 5 mos

▸ Verified ARM Cortex-M-based SoCs for consumer and set-top box platforms; pioneered secure-boot and low-power verification flows that became team-standard DV methodology.