Mauriya Ramaraj

Software Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience

Key Highlights

Expert in RISC-V architecture and hardware implementation.
Proven experience in optimizing machine learning computations.
Strong background in RTL design and functional verification.

Stackforce AI infers this person is a Hardware Engineer specializing in RISC-V architecture and machine learning optimization.

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Skills

Core Skills

Risc-vHardware Implementation

Other Skills

Sparse Matrix MultiplicationRTL DesignEDAComputer ArchitectureVery-Large-Scale Integration (VLSI)Functional VerificationField-Programmable Gate Arrays (FPGA)SystemVerilogC (Programming Language)Python (Programming Language)VerilogMATLAB

Experience

1 yr 11 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 11 mos

Current Experience

Qualcomm

3 roles

Engineer

Promoted

Dec 2025 – Present · 6 mos

Associate Engineer

Jul 2024 – Dec 2025 · 1 yr 5 mos

Interim Engineering Intern

Jan 2024 – Jun 2024 · 5 mos

Centre for heterogeneous and intelligent processing systems

Project Intern

Apr 2022 – Jan 2024 · 1 yr 9 mos · Bengaluru, Karnataka, India

Building a Brain Float FPU (16 bit) for a RISC V processor in order to optimize computations used in Machine Learning.
Worked on Hardware Implementation and Acceleration of Sparse Matrix Multiplication in COO format (Implemented COO Column product, Row product and Outer product).

RISC-VHardware ImplementationSparse Matrix Multiplication