Dec 2018 – Jan 2025 · 6 yrs 1 mo · Bengaluru, Karnataka, India · On-site

• Managed the entire Client Graphics Line, successfully delivering multiple SoCs to market, including the Intel ARC processor.
• Spearheaded the team in driving Physical Design of SoC, collaborating with multiple stakeholders to achieve project closure.
• Assembled and mentored a team from scratch, scaling the engineering team to meet project demands.

May 2005 – Nov 2018 · 13 yrs 6 mos · Bengaluru Area, India

• Managed a 7nm microprocessor project with a team of 40 people to be integrated into a Client SOC.
• Primary roles involve
• o Technical management and scheduling
• o Establish goals and metrics to be met by the team and ensure that the team executes to these
• goals
• Successfully completed delivery of a 16nm & 14nm core product for Game consoles
• o Gained customer confidence and respect by delivering the core on schedule and
• meeting/beating power performance benchmarks
• o Silicon results showing frequency upgraded by 10% and low power
• o Oversaw delivery, integration, and execution of the chip, interacted with 3 different SOC
• teams, providing program metrics/reports
• Managed a cross-site team in the integration of the 28nm client SoC chip
• o Involved in determining the schedule, resource planning, tracking of IP deliverables, liaising
• with other functional teams and management.
• o Worked with the team in resolving Design, Timing and Electrical Analysis
• Successfully delivered a 32nm Flagship server design team which was done cross-site and taken
• the chip to production
• o Resulted in significant revenue increase by power improvements along with frequency uplift.
• o Responsible for Bumps/Package, floor planning, power planning, placement, timing
• and electrical analysis, and physical verification checks – LVS, DRC leading to Tapeout.
• Delivered successfully multiple 45nm server and desktop designs
• o Incorporated significant Floor plan optimizations resulting in an overall SoC die area
• reduction of 17%.
• o Owned all the physical design activities from RTL to GDS
• Mentored and drove assimilation programs for new college graduates of the team and ramping up
• the design team
• Developed business process for SoC design methodology with reuse of IPs for doing multiple SoC
• chips in parallel

Nov 2003 – May 2005 · 1 yr 6 mos · Bangalore

• Delivered a USB2.0 IP design for the 65nm SoC chip used in the wireless products.
• Delivered the IP with special emphasis on power and performance with added importance on the
• floor plan as well.

Jan 1998 – Jan 2003 · 5 yrs · Austin

• Responsible for design of Trace Cache Control blocks including the 4-way TLB and 8-way TAGs
• in a 64-bit next-generation chip.
• o Involved floor planning, placement, and timing analysis.
• Delivered the full custom-design and integration of Clock (CK) control logic of the Opteron
• microprocessor.
• o Reduced the overall area of the block by greater than 10%.
• Responsible for enhancements to bus unit (BU) and floating-point units (FPU) that yielded
• improvement to product performance (greater than 10% in speed).
• o Spearheaded cross-functional effort in the re-design of the Icache that resulted in
• improving power dissipation and speed of the block by 20%.
• Validated functional units of various peripherals attached to the 8051 micro-controllers in the v493-
• VTECH chip used in a cordless phone.