Nikhil Naik

Software Engineer

Bengaluru, Karnataka, India14 yrs 1 mo experience

Highly Stable

Key Highlights

Over 5 years of ASIC engineering experience.
Expertise in SOC design and integration at leading tech companies.
Proven track record in RTL design and verification.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with a focus on SOC design and verification.

Contact

Skills

Core Skills

Soc Design Life CycleSoc IntegrationRtl DesignFunctional Verification

Other Skills

MakefileQC ToolsPerlI/O timingfloorplanpackagingbootDFTVerilogSystem VerilogScripting expertiseRTL VerificationCVLSIC++

About

With over half a decade of experience in ASIC engineering, my journey has been marked by a steadfast dedication to SOC design and integration. At NVIDIA, my role encompasses leveraging Verilog expertise and RTL design skills to advance cutting-edge graphics technologies. Our team's success is anchored in a collaborative approach to RTL verification, ensuring the highest quality in our products. My tenure at Intel as a SOC Design Engineer honed my technical competencies, where I contributed significantly to the development of SOC chips used in various mobile systems. The skills I cultivated there are now instrumental in driving innovations at NVIDIA. My goal is to continuously push the boundaries of SOC design, ensuring our technological solutions are not only efficient but also transformative for the industry.

Experience

14 yrs 1 mo

Total Experience

2 yrs 8 mos

Average Tenure

7 mos

Current Experience

Qualcomm

Staff Engineer

Nov 2025 – Present · 7 mos · Bengaluru, Karnataka, India · On-site

Working as CPUSS design Engineer

Nvidia

Senior Asic Engineer

Sep 2020 – Jun 2025 · 4 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

MakefileSOC IntegrationQC ToolsSOC design life cyclePerl

Intel corporation

SOC design Engineer

Feb 2018 – Aug 2020 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Qualcomm

Senior Engineer

Oct 2016 – Feb 2018 · 1 yr 4 mos · Bengaluru, Karnataka, India

Padring and TLMM owner for SOC
Worked on Qualcomm’s flagship 900 and 1000 series for design of MSMs.
Owner of the Padring and TLMM (GPIO) for two SoC chips used in Mobile Systems Module.
Developed pad muxing placement, interrupt controls, address mapping and the commands for registers used for pad controls.
Worked closely with I/O timing, SoC integration, floorplan, packaging, boot and DFT teams to provide the pad placement and boundary scan information.

Intel corporation

Graphics Hardware Engineer

Jul 2013 – Sep 2016 · 3 yrs 2 mos · Bengaluru, Karnataka, India

RTL Designer and Validator.
Design Complexity: Arbitration protocols, FSMs and Memory Management coding in Verilog.
Design of scalable modules, Power and Gate count saving.
Validation Experience: Protocol validation, Memory Management using System Verilog. Injectors, Checkers, Trackers, Checkers, BFM coding, behavioral modeling, Scripting expertise.
Timing: Physical Design Rep for Cluster. Synthesis and timing report generation.