Mar 2024 – Present · 2 yrs 3 mos · Greater Bengaluru Area · Hybrid

• Working in Intel’s GPU Display team, focusing on Display Message Unit (DMG) and HDCP blocks. My role spans system-level verification, UVM-based testbench development, feature/functional verification, coverage closure, and complex debug. I also have experience in formal verification using JasperGold, along with hands-on expertise in SystemVerilog, UVM, Synopsys VCS, and industry-standard verification workflows for high-performance GPU display architectures.