Abhilash Kulkarni — Software Engineer

Have 5+ years of experience in Physical Design. • Hands-on Physical Design experience in Floor planning, Power Planning, CTS, Place and Route, Static Timing Analysis, Signal Integrity /Cross-talk analysis, IR Drop and EM Analysis and Physical Verification using industry standard tools. • Have worked on latest cutting edge chip design process technologies like 7nm, 14nm, 16nm and 28nm Responsibilities: • Involved in challenges by handling PD placement and timing with significant RTL changes. • Resolving issues with high cell density, gate count growth and routing congestion. • Worked with RTL team to fix timing critical paths in the design. • Analyzed timing and congestion issues in the design, implemented many ECO iterations to reach timing closure. • Fixed IR drop, EM, noise & physical verification issues. • DRC, LVS clean-up activities, Base layer and Metal layer DRC fixes and make the design short / open free.

Stackforce AI infers this person is a Physical Design Engineer with expertise in semiconductor design and verification.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 5 mos