Durgesh Kumar Dubey — Product Engineer

Approx. 5.5+ years of experience in VLSI sector which comprises of Layout development and verification for Embedded MRAM, SRAM and ROM memory compilers. Sound knowledge about Device Physics and Fabrication steps while working in FINFET/CMOS/FDSOI technology. Worked on technology node: FINFET technology of 16nm, 14 nm & 10nm and CMOS technology of 40nm & 28nm, FDSOI technology of 28nm Worked for different foundries like INTEL, TSMC, UMC, GF, SAMSUNG etc. Responsibilities Handled: • Floor Planning, placement and routing on leaf-cell level as well as memory instance level in coordination with circuit design engineers. • ECO implementation and verification. • Good knowledge of all layout constraints which include: EM & IR, Antenna Effects, Latch up Effect, WPE, DFM Implementation, DRC, LVS, LVL, ERC, RC Extraction etc. • Hands on experience of many development and verification related tools. (Virtuso,CDesigner, Calibre, Hercules, ICValidator, Star RC, HSIM-RA etc.) and routing tools of INNOVUS. • Good knowledge of basic Unix Scripting.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor memory technologies.

Location: Noida, Uttar Pradesh, India

Experience: 12 yrs 6 mos