Prajwal Mishra — Intern

M.Tech VLSI Design graduate with industry experience in front-end design automation and Synthesis. Strong foundation in RTL analysis, synthesis flows, and tool-based design validation using industry-standard EDA tools such as Synopsys Fusion Compiler, RTL Architect, and Cadence Genus/Innovus. Hands-on experience across low-power ASIC design, clocking systems, and physical design methodologies, complemented by prior professional experience at Wipro. Adept at collaborating in cross- functional teams, ensuring design robustness, and applying strong problem-solving skills to complex semiconductor design challenges.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and EDA tools.

Location: Bengaluru, Karnataka, India

Experience: 1 yr 10 mos