Darshan Umesh

Lead IOS Developer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

In-depth knowledge of ASIC flow and physical design.
Hands-on experience with 40nm technology node.
Proficient in static timing analysis and physical verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and Physical Design.

Contact

Skills

Core Skills

Physical DesignAsic

Other Skills

Application-Specific Integrated Circuits (ASIC)FloorplanningPower AnalysisDesign Rule Checking (DRC)PlacementClock Tree SynthesisLayout Versus Schematic (LVS)Physical VerificationStatic Timing AnalysisVerilogAPR flowRoutingCMOSLogic DesignSynopsys IC Compiler

About

A Motivated Physical Design Trainee with In-depth Knowledge of ASIC flow, Physical design, and Static Timing analysis (STA). Performed APR Block Level Implementation (Floorplanning, Power planning, Placement, CTS, Routing) on 40nm Technology node and verified for DRC, LVS, and Antenna issues.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Samsung semiconductor

IP Design Intern

Jul 2025 – Present · 11 mos · Bengaluru, Karnataka, India · On-site

Rv-vlsi vlsi and embedded systems design center

Physical Design Engineer Trainee

Dec 2022 – Jul 2023 · 7 mos · Bengaluru, Karnataka, India · On-site

Technology: 40nm, Macro Count: 34, Standard cell count: 38403, Supply voltage: 1.1V, Power Budget: 600mW, Clock frequency: 833MHz, IR drop: (VDD+VSS): 5%.
Designing a Floorplan by determining macro placement as per dataflow diagram, and fly lines, and using the macro guidelines in order to achieve contiguous core area and good utilization.
Building a Power plan to maintain power network connectivity and IR drop. Also ensuring that there were no missing vias, floating wires, or power-ground DRC violations.
Creating a placement block by inserting pre-placement cells, placement constraints, and sufficient spacings in order to control the congestion and DRC violations obtained.
Performing clock tree synthesis and optimization using classic, CCD flows and analyzing the tool's behavior by comparing the timing reports in both flows.
Rectifying the LVS errors like shorts which were obtained post-routing by removing the overlapped routes and doing manual routing wherever necessary.
Analyzing and resolving the antenna violations by inserting the metal jumper and the diode into the layout.
Understanding the timing reports at every stage of PD flow, finding the cause of timing violations, and how some of the violated paths are being reduced in later stages.

Physical DesignApplication-Specific Integrated Circuits (ASIC)ASIC