Almitra Pradhan

Product Manager

Sunnyvale, California, United States23 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Leader of R&D team for cutting-edge ESP product.
Expert in equivalence checking and symbolic simulation.
Proven track record in developing advanced CAD tools.

Stackforce AI infers this person is a Semiconductor R&D Leader with expertise in verification solutions and CAD tool development.

Contact

Skills

Core Skills

Equivalence CheckingSymbolic SimulationCad ToolsVlsi Design

Other Skills

Logic SynthesisVerilogStatic Timing AnalysisPhysical DesignTCLASICVHDLRTL designVLSISystemVerilogFPGALow-power DesignComputer ArchitectureSPICEEDA

About

I lead the R&D team for Synopsys' Equivalence Check product ESP. My team and I work on continuous innovations to keep ESP the leading product in the custom design equivalence check space! ESP is a formal equivalence check product for custom/compiled memories, standard cells and IOs. With ESP's powerful symbolic simulation technology, customers can verify their designs with full coverage quickly and with an easy setup. ESP provides a viable solution for customers to verify their custom designs exhaustively without time consuming binary vector generation. ESP's unique technology saves time as well as catches even the corner case design bugs. ESP's add on capabilities such as Power Integrity Verification, Redundancy Verification, Logical2Physical mapping provide an added value taking it beyond equivalence checking.

Experience

23 yrs 3 mos

Total Experience

7 yrs 9 mos

Average Tenure

17 yrs 1 mo

Current Experience

Leapforword

Member of Advisory Team

Jul 2017 – Aug 2020 · 3 yrs 1 mo · Mumbai Area, India

I volunteered as an Advisory member at this non-profit organization in matters of organization, mentorship and fundraising.

Synopsys

R&D Manager

May 2009 – Present · 17 yrs 1 mo · San Francisco Bay Area

I lead Synopsys' ESP product's R&D team and work with the entire product team to develop equivalence check verification solutions based on an powerful symbolic simulation engine for custom designs in semiconductor chip development such as memories, standard cells and IOs.

Logic SynthesisVerilogStatic Timing AnalysisPhysical DesignTCLASIC+12

University of cincinnati

Research Assistant

Sep 2004 – Jan 2009 · 4 yrs 4 mos

3+ years experience as a Research Assistant at the University of Cincinnati
Successfully developed and implemented CAD tools for analog circuit sizing, multi-objective optimization, parasitic-aware synthesis
Other areas of experience include physical synthesis, VLSI design, algorithm design, parallel computing