Ganesh Murugesan

Product Engineer

Bengaluru, Karnataka, India24 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Extensive experience in DFT and digital design.
  • Proficient in multiple programming languages for design verification.
  • Strong background in quality processes and documentation.
Stackforce AI infers this person is a DFT and digital design expert with extensive experience in semiconductor engineering.

Contact

LinkedIn

Skills

Core Skills

DftDesign For TestabilityDigital DesignLogic Design

Other Skills

SCAN InsertionAutomatic Test Pattern GenerationJTAG InsertionCustomized MBIST InsertionEquivalence checkingPerl/Awk/Sed programmingVerilogVHDLQuality processDocumentation

Experience

24 yrs 6 mos
Total Experience
3 yrs
Average Tenure
5 yrs 3 mos
Current Experience

Qualcomm

2 roles

DFT

Mar 2021 – Present · 5 yrs 3 mos · Bengaluru, Karnataka, India

DFT

Jun 2013 – Sep 2019 · 6 yrs 3 mos

Marvell semiconductor

DFT

Sep 2019 – Mar 2021 · 1 yr 6 mos · Greater Bengaluru Area

  • DFT

Intel corporation

Senior DFX Engineer

Jun 2011 – Jun 2013 · 2 yrs

  • DFX

Rambus, bangalore

Senior Member Technical Staff - II

May 2008 – Jun 2011 · 3 yrs 1 mo

  • DFT

Montalvo systems, santa clara

DFT Engineer - II

Jun 2007 – Apr 2008 · 10 mos

  • DFT

Purple vision technologies pvt. ltd

Senior Staff Engineer

Oct 2003 – May 2007 · 3 yrs 7 mos · San Jose, California, United States

  • Worked as DFT Consultants in Texas Instruments (Bengaluru, India), Rambus (San Jose, USA), Cisco Systems (Milpitas, USA)
  • DFT (Design for Testability) Architecture Design & Implementation
  • SCAN Insertion, Automatic Test Pattern Generation (ATPG) and verification
  • JTAG (1149.1 and 1149.6) Insertion and verification
  • Customized MBIST Insertion and Verification
  • Equivalence checking
  • Perl/Awk/Sed programming
DFTDesign for TestabilitySCAN InsertionAutomatic Test Pattern GenerationJTAG InsertionCustomized MBIST Insertion+2

Accel software and technologies ltd

Staff Engineer

Oct 2001 – Oct 2003 · 2 yrs

  • Verilog/VHDL coding, simulation and verification
  • Logic Design and RTL coding
  • Digital Design and FSM based system design
  • Quality process and Documentation
VerilogVHDLLogic DesignDigital DesignQuality processDocumentation

Education

Manipal Academy of Higher Education

MS — VLSI-CAD

Jan 2008 – Jan 2011

University of Madras

BE — Electrical & Electronics Engineering

Jan 1997 – Jan 2001

Kendriya Vidyalaya

Jan 1983 – Jan 1996

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