B

Bindu K N

Software Engineer

Bengaluru, Karnataka, India14 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Functional Verification and Verilog.
  • Proven leadership in semiconductor engineering roles.
  • Strong educational background in Electronics and Communications.
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in Functional Verification and UVM methodologies.

Contact

Skills

Core Skills

Functional VerificationVerilog

Other Skills

GLSLogic verificationUniversal Verification Methodology (UVM)Formal VerificationSystemVerilogASICApplication-Specific Integrated Circuits (ASIC)CPerlSpecmanNCSimModelSimTcl-Tk

About

Senior Staff Engineer with a demonstrated history of working in the computer software industry. Skilled in Specman, Perl, Functional Verification, Verilog, and NCSim. Strong engineering professional with a Bachelor of Engineering (BE) focused in Electronics and Communications Engineering from Siddaganga Institute Of Technology.

Experience

14 yrs 6 mos
Total Experience
2 yrs 10 mos
Average Tenure
3 yrs 9 mos
Current Experience

Infineon technologies

Senior Staff Engineer

Sep 2022Present · 3 yrs 9 mos · Bengaluru, Karnataka, India

GLSLogic verificationFunctional VerificationVerilog

Cadence design systems

2 roles

Principal Design Engineer

Oct 2020Aug 2022 · 1 yr 10 mos

Universal Verification Methodology (UVM)Functional VerificationVerilog

Lead Design Engineer

May 2017Oct 2020 · 3 yrs 5 mos

Universal Verification Methodology (UVM)Functional VerificationVerilog

Samsung semiconductor india r&d

2 roles

Technical Lead

Apr 2017May 2017 · 1 mo · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)Functional VerificationVerilog

Lead Engineer

Apr 2015Mar 2017 · 1 yr 11 mos · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)Functional VerificationVerilog

Samsung r&d institute india

Senior Hardware Engineer

Jul 2013Mar 2015 · 1 yr 8 mos · Bangalore

Universal Verification Methodology (UVM)Functional VerificationVerilog

Wipro technologies

VLSI Engineer

Jul 2011Jun 2013 · 1 yr 11 mos · Bengaluru Area, India

Education

Siddaganga Institute Of Technology

Bachelor of Engineering (BE) — Electronics and Communications Engineering

Jan 2007Jan 2011

Stackforce found 100+ more professionals with Functional Verification & Verilog

Explore similar profiles based on matching skills and experience