Rameez KT — Software Engineer
Working as Digital IC Design Verification Engineer at MaxLinear. Skills : UVM, SystemVerilog, Perl and Python Scripting, Verilog.
Stackforce AI infers this person is a Digital IC Design Verification Engineer with expertise in VLSI and ASIC industries.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 9 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
Career Highlights
- Expert in Digital IC Design Verification.
- Proficient in UVM and SystemVerilog.
- Strong background in VLSI and ASIC design.
Work Experience
MaxLinear
Staff Engineer (3 yrs 4 mos)
Design Verification Engineer (2 mos)
FrenusTech Pvt Ltd
Senior Hardware Design Engineer (6 mos)
Hardware Design Engineer (4 yrs 11 mos)
Rambus
ASIC Design Verification Engineer (3 yrs 3 mos)
Education
Bachelor of Technology - BTech at Rajiv Gandhi Institute of Technology, Kottayam
