Viyaash V.

Software Engineer

Delhi, India2 yrs 2 mos experience

Key Highlights

Experienced in ASIC design and validation.
Hands-on experience in semiconductor fabrication.
Strong foundation in digital VLSI design.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with a focus on ASIC and VLSI design.

Contact

Skills

Core Skills

Asic DesignDigital Circuit DesignSystem On Chip DesignSemiconductor FabricationSemiconductor ProcessingDevice Simulation

Other Skills

RTL developmentsynthesisvalidationPHY PMA IPsPCIe Gen6/7Ethernet data ratesSoC designARM Cortex M3RISC-Vchip fabricationsurface characterizationmetrologypattern damage analysislithographyetching

Experience

2 yrs 2 mos

Total Experience

1 yr 2 mos

Average Tenure

1 yr

Current Experience

Synopsys inc

2 roles

ASIC Engineer

Jun 2025 – Present · 1 yr · Noida, Uttar Pradesh, India · On-site

End-to-end RTL development and synthesis of testchips for validation of PHY PMA IPs, supporting PCIe Gen6/7 and Ethernet data rates.

RTL developmentsynthesisvalidationPHY PMA IPsPCIe Gen6/7Ethernet data rates+2

Intern (Technical-Engineering)

Jan 2025 – May 2025 · 4 mos · Noida, Uttar Pradesh, India · On-site

Indraprastha institute of information technology, delhi

Teaching Assistant, Digital VLSI Design ECE314/ECE514

Aug 2024 – Dec 2024 · 4 mos

Digital VLSI Design is a UG/PG course offered by Dr. Anuj Grover. The course introduces students to CMOS circuits, performance and power estimation of circuits, combinational and sequential circuit design, design of datapath and memory subsytems.

Purdue university

Semiconductor Fabrication Research Intern

Jul 2024 – Aug 2024 · 1 mo · West Lafayette, Indiana, United States · On-site

Guides: Dr. David Janes, Dr. Arnold Chen
Acquired hands-on experience in chip fabrication. Worked on surface characterization (metrology) of patterned Ti and Cr metallized wafers, identified the impact of parameter and methodology variations and analyzed pattern damage.

chip fabricationsurface characterizationmetrologypattern damage analysisSemiconductor Fabrication

Indian institute of technology hyderabad

Semiconductor Fabrication Trainee

Jun 2024 – Jul 2024 · 1 mo · Hyderabad, Telangana, India · On-site

Guides: Dr. Naresh K Emani, Dr. Siva Vanjari
Demonstrated fundamental processes in lithography, etching, and deposition at Nano-X, IIT-Hyderabad. Learnt cutting-edge technology in the fabrication of FinFETs, GAAFETs and MOSFETs.

lithographyetchingdepositionFinFETsGAAFETsMOSFETs+1

Semiconductor laboratory (scl), meity, govt of india

Research Intern

May 2024 – Jun 2024 · 1 mo · Sahibzada Ajit Singh Nagar, Punjab, India · On-site

Guide: Mr. Anil Sharma
As a part of Technology Development Group (TDG), simulated I-V characteristics for AlGaN/GaN HEMTs, taking various parameters into consideration.

I-V characteristics simulationAlGaN/GaN HEMTsDevice Simulation