Srinath Jeevakumar

CEO

Bengaluru, Karnataka, India6 yrs 8 mos experience

AI Enabled

Key Highlights

Led performance verification for cutting-edge SoC at Nvidia.
Published IEEE paper on advanced verification frameworks.
Achieved significant performance boosts in Qualcomm DSP.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in performance analysis and silicon validation.

Contact

Skills

Core Skills

Performance VerificationSilicon Bring-upPerformance Analysis

Other Skills

ARM CHIARM AXIDMA enginePCIe bifurcationAI-assisted debugC (Programming Language)RTL simulationSilicon ValidationHWPMSystem PerformancePower ConsumptionStatistical AnalysisArchitectureBenchmarkingPerformance Measurement

About

Senior Verification Engineer with 5+ years at Nvidia, Qualcomm, and ARM, specializing in SoC/IP performance verification, functional verification, and silicon bring-up. IEEE-published author — "A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking" | VLSI-SoC 2022 What I do: --> At Nvidia, owned end-to-end verification for Vera-Rubin data center SoC — driving DMA engine and PCIe bifurcation, Multi-engine test plan sign-off, HWPM/VPM infrastructure across RTL and silicon, while pioneering AI-assisted debug workflows using Cursor. --> At Qualcomm, owned performance characterization of Hexagon DSP across AI, Audio, and Modem IPs — closing correlation gaps to <5% and driving micro-architectural changes that boosted ML workload performance by 3–10% Core Skills: ARM CHI · ARM AXI · PCIe · UVM · SystemVerilog · C/C++ · Python · Performance Debug · Silicon Bring-up · AI-assisted Verification 📧 srinath1994.ceg@gmail.com | 📞 +91 86828 81734

Experience

6 yrs 8 mos

Total Experience

2 yrs 3 mos

Average Tenure

2 yrs 2 mos

Current Experience

Nvidia

Senior Architect

Apr 2024 – Present · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Executed SoC performance verification for Vera-Rubin data center SoC across RTL and silicon, ramping up on internal interconnect protocols and driving debug of complex protocol-level failures to unblock team progress.
Owned DMA engine and PCIe bifurcation test plan bring-up, debug, and issue closure across RTL through silicon, resolving critical functional and performance failures to meet sign-off bandwidth targets.
Led silicon validation for multi-engine traffic scenarios, debugged critical register and programming issues, and tuned DDA/NCM settings to achieve stable high DRAM utilization under stress workloads.
Owned HWPM/VPM-based monitoring and debug infrastructure across RTL and silicon, adding watchpoints, protocol-aware traffic models, and perf-mux flows for faster root-cause analysis.
Accelerated regression and debug turnaround for DMA, PCIe bifurcation, and HWPM by systematizing triage and resolving complex credit, tag, configuration, and ToT break issues.
Pioneered an AI-assisted debug and verification workflow using Cursor, standardizing LLM-driven root-cause analysis and code generation practices across teams — improving debug turnaround and establishing a reusable framework for efficient AI adoption in silicon verification.

Performance VerificationARM CHIARM AXISilicon Bring-up

Qualcomm

2 roles

Senior Engineer

Dec 2023 – Apr 2024 · 4 mos

C (Programming Language)Performance Analysis

Engineer

Jul 2021 – Dec 2023 · 2 yrs 5 mos

Performed performance verification of Qualcomm's Hexagon DSP processor, assessing its functionality across diverse IPs, such as Artificial Intelligence, Audio, Modem and Machine Learning.
Developed microbenchmarks by adapting key kernels from different applications to identify and address performance bottlenecks on RTL and simulators.
Detected micro-architecture bottlenecks during machine learning application emulation, proposing data-backed insights that led to improved micro-architecture changes and a 3%-10% performance boost in machine learning applications.
Analyzed and resolved correlation issues between RTL-ISS and Emulation-Silicon platforms to enhance performance predictions for next-generation cores.

C (Programming Language)Performance AnalysisPerformance Verification

Arm

CPU Design Verification Engineer

Jan 2021 – Jul 2021 · 6 mos · Bengaluru, Karnataka, India

Contributed to the design verification of a 64-bit ARM Cortex-A Processor.
Developed new test cases to assess micro-architectural advancements.
Successfully addressed UVM errors through tarmac dumps and waveform captures, leveraging knowledge of ARM instruction set architecture and micro-architecture for assistance.