Simon Southwell

CEO

Cambridge, United Kingdom35 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 35 years in R&D and engineering.
Expert in ASIC and FPGA design.
Active contributor to open-source projects.

Stackforce AI infers this person is a seasoned expert in ASIC and FPGA design within the telecommunications and embedded systems industries.

Contact

simon.southwell@gmail.com LinkedIn

Skills

Core Skills

System DesignDigital Ip DevelopmentEmbedded SoftwareDsp DesignIntegrated Circuit DesignAsic DevelopmentWireless TechnologyWireless CommunicationVerificationNetwork Interface DesignCo-simulationSoftware ModellingAsic VerificationIp DevelopmentData CompressionFpga Design

Other Skills

DSPCPU systems designmodellingLTE DSP designsystem modellingPHY embedded software3G/LTE digital designDigital ASIC developmentlow power ZigBee wirelesssystem and IP specificationWireless LAN MAC designintegration of digital WLAN IPPCI-Express 2.0 endpoint interfaceIP verificationTricore 2 instruction set simulation

About

Engineer with more than 35 years of experience in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now semi-retired, spending time contributing IP to the open-source community and sharing my experience and knowledge through writing articles and mentoring undergraduates and junior engineers. I have a particular interest in processor systems and sub-systems, system modelling in software and co-simulation. I am also a collaborator on the OSVVM project, adding and supporting co-simulation capabilities. Areas of experiences include original logic IP design for ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking, embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11) and more. #soc #chipdesign #fpga #asic #cpu #processors #riscv #logic #verilog #vhdl #verification #simulation #pli #interconnect #embeddedsoftware #embeddedsystems #operatingsystems #linux #cellular #wirelesscommunications #algorithms #dsp #articles #documentation #mentoring #osvvm #cosimulation

Experience

35 yrs 4 mos

Total Experience

3 yrs 2 mos

Average Tenure

5 yrs 1 mo

Current Experience

Retired

May 2021 – Present · 5 yrs 1 mo

Global inkjet systems ltd (gis)

2 roles

Logic Architect

Jun 2020 – May 2021 · 11 mos

FPGA Firmware Design Engineer

Nov 2017 – Jun 2020 · 2 yrs 7 mos

On sabbatical

Systems Designer

Aug 2016 – Oct 2017 · 1 yr 2 mos

Systems Designer on sabbatical, doing researches on various interests, including DSP, CPU systems design, modelling and digital IP development, and now looking for the next opportunity.

DSPCPU systems designmodellingdigital IP developmentSystem DesignDigital IP Development

U-blox

Senior Principal Engineer

Jun 2014 – Jul 2016 · 2 yrs 1 mo · Melbourn, Cambridgeshire, U.K.

Senior Principal Engineer working on LTE DSP design, system modelling and PHY embedded software

LTE DSP designsystem modellingPHY embedded softwareEmbedded SoftwareDSP Design

Blackberry

Integrated Circuit Design Engineer

Mar 2013 – May 2014 · 1 yr 2 mos · Harston, Cambridgeshire, U.K.

IC Design Engineer working on 3G/LTE digital design

3G/LTE digital designIntegrated Circuit Design

Silicon laboratories (fomerly ember)

Staff Design Engineer

Sep 2010 – Feb 2013 · 2 yrs 5 mos · Cambridge, U.K.

Digital ASIC development on low power ZigBee wireless: system and IP specification, developing baseband and MAC logic, digital emulation of product and software/hardware boundary specification.

Digital ASIC developmentlow power ZigBee wirelesssystem and IP specificationASIC DevelopmentWireless Technology

St-ericsson (formerly stmicroelectronics)

Principal Design Engineer

Sep 2007 – Dec 2009 · 2 yrs 3 mos · Bristol, U.K.

Wireless LAN MAC design and verification lead engineer. Responsible for integration of digital WLAN IP, and regression environment and testing. Support for synthesis to target both target library and FPGA (for verification and firmware development)

Wireless LAN MAC designverificationintegration of digital WLAN IPWireless CommunicationVerification

Quadrics supercomputers world

2 roles

Senior Engineer

Apr 2002 – Apr 2007 · 5 yrs · Bristol, U.K.

PCI-Express 2.0 endpoint interface specification and design for network interface card. Co-simulation/PCI-e host model for IP verification and simulation of Linux enviornment for S/W development. Internal accelerator IP block implementation and verification.

PCI-Express 2.0 endpoint interfaceco-simulationIP verificationNetwork Interface DesignCo-simulation

Senior Engineer

Jan 1998 – Jan 2001 · 3 yrs · Bristol, U.K.

Network switch ASIC verification. DDR SDRAM interface IP development for network interface chip and proprietry link protocol specification upgrades and implementation.

ASIC verificationDDR SDRAM interface IP developmentASIC VerificationIP Development

Infineon

Senior Software Engineer

Jan 2001 – Apr 2002 · 1 yr 3 mos · Bristol, U.K.

Development engineer in hardware modelling group, responsible for Tricore 2 instruction set simulation model, co-simulation of modelling environment with HDL simulation tools and specification of cycle accurate Tricore models.

Tricore 2 instruction set simulationco-simulation of modelling environmentSoftware ModellingCo-simulation