Shreyas M O

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience

Key Highlights

4+ years in semiconductor validation and development.
Expertise in both pre-silicon and post-silicon validation.
Proficient in debugging with advanced tools and methodologies.

Stackforce AI infers this person is a Semiconductor Validation Engineer with extensive experience in embedded systems.

Contact

shreyasmo1999@gmail.com LinkedIn

Skills

Core Skills

Pre & Post Silicon ValidationEmbedded SystemsIp VerificationDigital ElectronicsVerification Methodologies

Other Skills

Embedded CI2CUARTSPIGPIOJTAGController Area Network (CAN)ZebuAutomotive SoCYocto linuxX86Client PCCANHigh speed peripheralsLow speed peripherals

About

Motivated engineering professional with 4+ years of experience in leading semiconductor companies. Have hands on expertise in embedded systems, pre-silicon and post-silicon validation, firmware driver development on platforms such as Intel x86_64 SoCs and Google’s tensor chips. Demonstrated ability to collaborate effectively with geographically diverse teams, adapt quickly to new technologies and solve complex challenges. Extensive experience in functional silicon validation of UFS (high-speed storage protocol IP) and low-speed IOs (UART, SPI, QSPI, I2C, GPIO & CAN). Basic understanding on PCIe Gen5/Gen6 protocol and strong understanding of silicon validation frameworks and bare metal FW test infrastructure development. Proficient in debugging using tools such as Verdi, trace32 Lauterbach (JTAG) and analyzers.

Experience

2 yrs 9 mos

Total Experience

1 yr 2 mos

Average Tenure

5 mos

Current Experience

Qualcomm

Senior Silicon Validation Engineer (GPU/System)

Jan 2026 – Present · 5 mos · Bengaluru · On-site

Intel corporation

SoC Validation Engineer

May 2024 – Jan 2026 · 1 yr 8 mos · Bengaluru · On-site

Project: Intel’s Client PC SoC
● Contributed to validation of I2C, UART and ISH (Integrated Sensor Hub) IPs across multiple PCH silicon stepping with real-time bring-up
● Validated interrupt controller (APIC) functionality and interrupt routing across SoC subsystems
● Collaborated with RTL, architecture, Design verification teams for issue reproduction, root-cause analysis, and bug tracking using JIRA
Project: Automotive SoC
● Developed and executed bare-metal test cases in Embedded C to validate RTL functionality of CAN controller (ISO 11898), I2C, UART and GPIO IP blocks for Pre & Post-Silicon validation
● Performed functional validation on Zebu Emulation platform with Verdi waveform debugging

Pre & Post Silicon ValidationEmbedded CI2CUARTSPIGPIO+8

Google

Silicon Validation Consultant

May 2022 – Apr 2024 · 1 yr 11 mos · Bengaluru, Karnataka, India

(Through Mettlesemi Systems and Technologies)
Project: Google Tensor Chips
● Performed compliance and functional validation of UFS-4 Controller on Google Tensor SoC using lightweight real-time operating systems(Little Kernel) frameworks
● Developed JEDEC protocol-level validation tests, monitored bus activity using analyzers, and captured issues through waveform analysis
Project: Google Pixel Buds
● Conducted Pre and Post Silicon validation for peripherals including I2C, QSPI, SPI, UART, and GPIO
● Validated peripherals on FPGA and silicon using FTDI devices and Saleae analyser tool
● Conducted DVFS testing and TRNG characterization on silicon using temperature chambers
● Debugged issues using trace32 Lauterbach (JTAG) and Verdi tools on Zebu emulation platform