Sukruth S

Product Manager

Bengaluru, Karnataka, India4 yrs 5 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Published 6+ papers in top journals
Expertise in PLL and VCO design
Developed AI tools for chip verification

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed-Signal IC design.

Contact

suksidd@gmail.com LinkedIn

Skills

Core Skills

Analog Integrated Circuit DesignEngineering LeadershipMixed-signal Ic DesignCircuit DesignAnalog Circuit Design

Other Skills

Analog ModelingMixed-Signal Integrated CircuitsLinuxRF CircuitsSerDesPython (Programming Language)Semiconductor FabricationMATLABField-Programmable Gate Arrays (FPGA)Artificial Intelligence (AI)RTL Design

About

Driven Analog IC Design Engineer with 4+ years of experience in analog design and mixed-signal verification. Strong background in PLL, VCO, comparators, error amplifiers, bandgap references, and high-speed PHY circuits. Proficient in Cadence Virtuoso, Spectre, Synopsys Custom Compiler, Verilog-A/AMS, and Python scripting. Published 6+ papers in top international journals on semiconductor physics and IC design. Currently seeking Analog IC Design roles in Europe to apply advanced design expertise.

Experience

4 yrs 5 mos

Total Experience

1 yr 6 mos

Average Tenure

Current Experience

Cadence

Lead Design Engineer

Aug 2024 – Nov 2025 · 1 yr 3 mos · Europe · Hybrid

My primary responsibilities include the design and development of calibration blocks, such as ZQ calibration circuits, ensuring precise impedance control for optimal DDR performance.
Additionally, I focus on analog modeling, enhancing simulation accuracy and design efficiency.

Analog Circuit DesignEngineering LeadershipAnalog ModelingAnalog Integrated Circuit Design

Synopsys inc

2 roles

Senior Analog Design Engineer

Feb 2024 – Sep 2024 · 7 mos

Circuit DesignMixed-Signal IC DesignMixed-Signal Integrated CircuitsAnalog Integrated Circuit Design

Analog/Mixed signal Engineer

Aug 2022 – Feb 2024 · 1 yr 6 mos

Working in the Highspeed PHY SerDes team in Solutions group at Synopsys.
Extracted and reviewed power, EMIR and bias test benches as well as the subsequent reports for various sub blocks as well as top level schematic for a range of IPs.
Responsible for RTL and Analog verification, primarily between the interconnects between PCS and PMA of SERDES designs such as functional and formal testbench verification.
Carried out more than 28 Verification test plans on TX, RX and Supporting blocks of both enterprise and consumer IP PHY with 15 test cases for each block such as bacon, Datapath etc with responsibilities including testbench creation, simulation, bug fixing and functional verification of overall PCS and PMA.
Worked on designing buffers, Current mirrors and VCO in the RX Sub block.
Derived and customised 8GHz and 18GHz PLL analog subblocks for various enterprise Serdes such as E16, E25 and C8 Serdes IPs

Mixed-Signal IC DesignLinuxRF CircuitsSerDesAnalog Circuit Design

Texas instruments

Analog Design Engineer

Jan 2022 – Jul 2022 · 6 mos · Bangalore Urban, Karnataka, India

Developed an AI based verification tool from the ground up using python libraries to help in easy sign off of chip debug.
Engineered novel circuit modules for various TI sub blocks such as ILIM IMON in efuse and ideal diode controller chip using machine learning algorithms. The modules outperformed previous iterations by 55% per cent.

Mixed-Signal IC DesignLinuxPython (Programming Language)Analog Circuit Design