Gaurav Singh

Software Engineer

West Delhi, Delhi, India20 yrs 6 mos experience

Highly Stable

Key Highlights

Over 15 years of experience in software development.
Expert in optimizing performance for complex software tools.
Led engineering teams in delivering EDA products.

Stackforce AI infers this person is a seasoned EDA and telecommunications software architect with extensive optimization expertise.

Contact

Skills

Core Skills

C++Eda Software DesignVlsi Soc DesignCompile Time OptimizationRtl SimulationPerformance OptimizationDatabase ManagementCoverage Analysis

Other Skills

Software developmentPartitioning algorithmDynamic test loadingPredictive event samplingCode generation optimizationsCoverage database designSQL databaseXML schema implementationGSMGNU DebuggerMultithreadingClearCaseProgrammingXMLSystemVerilog

About

Technical leader with over 15 years of total experience in designing and developing complex computational software and large-scale software systems. Over 3+ years of experience in leading engineering team to deliver best in class product in EDA domain. Adept in handling software complexities where CPU performance and memory foot print are critical. Strong expertise in C, C++, Data Structures, SQL, HDL (verilog), OS internals and Computer Architecture. Specialties: • C/C++ programming. • STL, Boost Libraries. • OOAD Design Patterns. • RDMS client server interactions in multithread/multiprocess environment. • Customized in-memory database interface management. • Identifying the performance bottlenecks in complex software tools and implementing the solutions to optimize the performance of tool.

Experience

20 yrs 6 mos

Total Experience

5 yrs 3 mos

Average Tenure

4 yrs 8 mos

Current Experience

Cadence design systems

Software Architect

Oct 2021 – Present · 4 yrs 8 mos · New Delhi, Delhi, India

Design and development of EDA software.

C++EDA software designSoftware development

Synopsys inc

2 roles

R&D Engineer Senior Staff

Promoted

Dec 2019 – Oct 2021 · 1 yr 10 mos · Noida Area, India

VCS logic simulator: Synopys
Role: Technical leader responsible for scaling up the core simulation engine to handle VLSI SoC (System on chip) designs with trillions of gates.
Key Contributions:
Designed and developed partitioning algorithm to partition the design in smaller chunks which can be compiled in parallel on same or different machine on the farm. Improved the TAT (Turn Around Time) by a factor of 10x for large designs.
Designed and developed new dynamic test loading paradigm, to improve compile time for large designs.Improved the disk space usage by 20x, compile time by 5x for large designs.

VLSI SoC designPartitioning algorithmDynamic test loadingCompile time optimization

R&D Engineer Staff

Mar 2017 – Dec 2019 · 2 yrs 9 mos · Noida Area, India

Cadence design systems

4 roles

Senior Member Of Consulting Staff

Jul 2016 – Mar 2017 · 8 mos

IUS logic simulator: Cadence
Role: Individual contributor responsible for improving the runtime performance of RTL simulation core engine.
Key Contributions:
Designed and developed a predictive event sampling scheme for sequential user defined primitives, to reduce the number of events at simulation. Improved the runtime by 10%.
Implemented code generation optimizations of vectorization and loop interchanging and loop unrolling to improve runtime performance by 10%.

RTL simulationPredictive event samplingCode generation optimizationsPerformance optimization

Member of Consulting Staff

Jul 2013 – Jun 2016 · 2 yrs 11 mos

IES coverage database: Cadence
Role: Individual contributor with component ownership of coverage database and its integration with other tools.
Key Contributions:
Scaled the coverage database for billions of coverage nodes and 24x7 flow, designed and developed coverage SQL database from scratch using master-slave architecture. Initial feasibility study and proof-of-concept done in Java using Hibernate framework, final implementation done in C++.
Designed and developed 3rd party coverage data importer. Defined an XML schema based on coveragedatabase UCIS standard and implemented a scalable and optimal application using Apache-Xerces xml parser.
Optimized coverage database merge functionality by using selective deep copying of complex
hierarchies (of database elements) to improve the merge time by 30% and reduce the merged coveragedatabase size on disk by 40%.
Unified the coverage metrics across various verification engines (simulation/formal/emulation). Enabled merging of Coverage Database dumped by various verification engines by implementing a newchecksum-based merge functionality.

Coverage database designSQL databaseXML schema implementationDatabase managementCoverage analysis

Senior Member of Technical Staff

Jul 2011 – Jun 2013 · 1 yr 11 mos

Member of Technical Staff

Apr 2010 – Jun 2011 · 1 yr 2 mos

Aricent

Senior Software Engineer

Aug 2005 – Mar 2010 · 4 yrs 7 mos · Gurgaon, India

FlexiEdge & FlexiMulti 2.5G BTS: Aricent
Role: Individual contributor worked on the Abis E1/T1 Interface termination at BTS, TCP/UDP protocols used to route voice/data call frames in the multicore multithread embedded system.
Key Contributions:
Designed and developed timer and queue manager modules to buffer and time GSM/GPRS frames as per GSM frame timing.
Designed and developed a GSM/GPRS frame parsing algorithm using the pre-computed metadata about the frame bits for various GSM/GPRS frames.