Naveen K. — DevOps Engineer

Currently working as Silicon Validation Engineer with Intel, Bangalore • Hands-on experience in Initial Board bring-up activities for the virgin silicon. • Good understanding of ARM architecture • Involvement in Test case Development & Execution of the patterns directly on Silicon chip. • Automate the validation process using FPGA and Python to enhance the coverage. • Expert in handling and Generating Sweeping scenario and automate them. • Automate different Lab equipment’s using Python • Hands-on experience with debugging tools like Lauterbach & other Lab equipment like logic analyzer and oscilloscope • Reading & understanding the board schematics for writing test cases/drivers and other debugging activities. • Analyze test results and identify potential issues, debug and root cause any silicon issues to improve quality and performance of circuits, hard and soft IPs • Familiarity in SOC level Debug troubleshooting, including hands-on experience with schematics, layout, and post-silicon debug

Stackforce AI infers this person is a Silicon Validation Engineer with expertise in Embedded Systems and Validation Engineering.

Location: Bangalore, Karnataka, India

Experience: 12 yrs 5 mos