Pravesh Rathee

DevOps Engineer

Noida, Uttar Pradesh, India6 yrs 7 mos experience

Highly StableAI Enabled

Key Highlights

Expert in DFT methodologies and low-power design.
Proficient in AI applications for edge devices.
Strong background in Semiconductor EDA tool development.

Stackforce AI infers this person is a Semiconductor and AI specialist with a focus on EDA tools and machine learning applications.

Contact

Skills

Core Skills

DftIeee1500C++Artificial Intelligence (ai)Rtl Design

Other Skills

Low-power DesignObject Oriented DesignOpenVINOVTuneNVIDIA NeMogRPCDockerKubernetesSpeech RecognitionNatural Language ProcessingMicroservicesClock Domain CrossingLanguage SkillsComputer LiteracyFront-end Coding

About

I am professional software developer with 4+ years of experience in Semiconductor EDA tool development , AI based workloads for edge devices. I offer my expertise in designing, developing , optimising and testing AI based features/applications in Electronic Design Automation, Multimedia(Video) and Audio Domains. TECHNICAL SKILLS: • Programming Languages: C++, oneAPI SYCL, Python, Verilog, TCL, Perl, Bash • Technology & Skills: Data Structures and Algorithm, Object Oriented Programming, GNU-Debugger, Microservices, Machine Learning, Computer vision, Natural Language Processing, Speech Recognition, Docker, Kubernetes, Multi-threading , Multiprocessing, Socket Programming, GStreamer Framework, Codecs. • Methodology: Agile (SCRUM).

Experience

6 yrs 7 mos

Total Experience

2 yrs 6 mos

Average Tenure

1 yr 6 mos

Current Experience

Cadence

2 roles

Lead DFT Engineer/CAD Engineer

Dec 2024 – Present · 1 yr 6 mos

1. Developed and maintained IEEE 1500-compliant core test methodologies, enabling standardized wrapper-based testing across multiple SoC designs.
2. Architected and implemented wrapper insertion flows for both power-aware (UPF/CPF) and non-power-aware designs, supporting multi-voltage and always-on domain requirements.
3. Designed a novel wrapper insertion architecture for low-power designs, addressing correlated logic power (CLP) violations and power-domain-aware dedicated wrapper cell placement.
4. Authored comprehensive methodology documentation for wrapper insertion in low-power and Launch-Off-Shift (LOS) based designs, serving as a reference for design teams.
5. Diagnosed and resolved DRC violations in scan insertion and wrapper insertion flows, improving first-pass DFT closure rates.
6. Built a Conformal LEC-based logical equivalence checking flow for post-DFT netlists, identifying functional issues in ~20% of designs pre-silicon — preventing potential hardware escapes.
7. Developed web-based dashboards to visualize wrapper insertion quality metrics across designs, enabling data-driven DFT signoff and coverage tracking.
8. Proficient in Cadence EDA tools: Modus (DFT insertion), Genus (synthesis), Innovus (P&R), Conformal (LEC), and Xcelium (simulation).

DFTIEEE1500

Lead Test Engineer

Dec 2024 – Present · 1 yr 6 mos

Develop test cases and new features for IEEE1500 core wrapper insertion flows for power aware, non-power-aware and 3DIC designs for hierarchical test flow at core level. Designed novel low-power wrapper architecture to reduce scan switching for ATPG patterns. Owned and resolved scan-wrapper DRC violations, LEC checks and low power CLP checks at core level. Generate ATPG patterns for stuck and delay tests for wrapper inserted designs at core level. Developed a web dashboard to benchmark wrapper insertion quality and runtime profiling metrics. Created methodology documentation for wrapper insertion in low-power and LOS-based designs, serving as reference for design teams. Built and integrated Claude SKILLS to help RnD to debug wrapper insertion issues. Working on hierarchical test flows (2-level and 3-level) and and pattern mismatch debugging.

Synopsys inc

2 roles

Staff Engineer/ Front End CAD & RnD

Jul 2023 – Nov 2024 · 1 yr 4 mos

1.1 Design, develop and optimize algorithms performance to improve hardware read time in multiprocessing enviroment.
1.2 Automate different LEC techniques and generate ECO's to get smallest ECO patch size.
1.3 Created automated script for DFT lec checks.
1.3 Write and maintain regression/unit tests of the tool to ensure correctness, reliability and maximum code coverage of the tool.

C++Object Oriented Design

Computer Aided Design Specialist

Jul 2023 – Nov 2024 · 1 yr 4 mos

Automated different ad-hoc techniques for designers which produced smaller ECO patches for incremental netlists. Maintained automation of LEC checks for post-DFT netlists, catching functional issues in 20̃% of designs pre-silicon and preventing hardware escapes. Work with product engineers and created regression test cases of the Formality ECO tool for different features.

Intel corporation

3 roles

AI Software Engineer

May 2020 – May 2023 · 3 yrs

1.1 Development of Proof of Concept for Robot Navigation using Live Speech Audio Audio using Gazebo .
1.2 Experience in building End-to-end Conversational AI application as Microservices.
Optimizing the Speech Recognition & Natural Language Processing models to enhance the
performance on Intel Architecture.
Developed end -to-end web based ASR - NLP- TTS microservice and deployed to
Kubernetes.
Integrated Noise Suppression feature in Speech Recognition Service.
Skills: OpenVINO · VTune · NVIDIA NeMo · gRPC · FineTuning · Quantization · Docker · Kubernetes
· Streamlit · Neural Network Compression · Post Training Optimization · Huggingface
· Optimum · Transformers
1.3 Develop End to End Video Analytics Applications taking input from IP cameras and store to
remote server using Computer Vision and multimedia API's.
Multiple IP camera streams were taken and their codecs and resolution were changed , run
Computer vision algorithms to display annotations on multiple displays. Implementations
targeted to use maximum hardware capability like Decoder Engine, Render Engine etc.
Skills: Object Detection · Classification · Video Codec(h264/h265) · Gstreamer · DLStreamer
· Tracking · VAAPI
1.4 Analyzed architectural bottlenecks for GPU/CPU on real world applications for IOT uses cases that
involve Deep Learning Models.
1.5 Developed Cryptographic Algorithm using OpenSSL to perform Encryption and Decryption.
Developed Cryptographic library for Multimedia Analytics.
Plugin can perform decryption & encryption on each frame of the raw video.

OpenVINOVTuneNVIDIA NeMogRPCDockerKubernetes+1

Artificial Intelligence Engineer

Promoted

Aug 2019 – May 2023 · 3 yrs 9 mos

Worked with hardware designers to automate the clock domain crossing runs to perform end-to-end CDC checks for SoC hardware and generate reports. The flow and report generation was automated using python, TCL and shared data report to respective IP owners. Designed and deployed text-to-speech, automatic speech recognition micro services using docker and kubernetes after fine tuning for lower latency and memory. Designed and optimized the video analytic pipelines with gstreamer elements and different deep learning models to meet specified KPI’s for stakeholders. Performed performance profiling for CPU, GPU and memory to identify the bottlenecks of the AI video analytic pipelines on different Intel SoC platforms. Implemented cryptographic and communication protocols for network video recorder system using cmake build system.

SoC Design Integeration / Automation Engineer

Aug 2019 – Apr 2020 · 8 mos

1. Worked as SoC Design Automation Engineer
Worked with other specialists that are members of SoC Design team to implement design/flows for SoC's.
Integerated various IPs and ensuring design meets DFT,CDC and power requirements.
Worked as CAD engineer and automated the CDC runs to reduce human intervention .
Develop & maintain design enablement methodologies.

Clock Domain CrossingRTL Design