R

Rajendra Kumar

Software Engineer

Noida, Uttar Pradesh, India21 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SystemVerilog and EDA tools.
  • Proven track record in behavioral synthesis enhancements.
  • Strong background in ASIC and SoC verification.
Stackforce AI infers this person is a highly skilled EDA engineer with expertise in ASIC and SoC design verification.

Contact

LinkedIn

Skills

Core Skills

SystemverilogEdaBehavioral SynthesisC++AsicSoc

Other Skills

Open VeraC APIsInfinibandLogic SynthesisPerlCEmulationAlgorithmsCompilersData StructuresVHDLLinuxMultithreadingSoftware DevelopmentEmbedded Systems

About

Software development engineer with proficiency in Developing and Debugging complicated hardware , software and their interaction . Having worked in all aspect emulation flow ( Frontend, Backend, Runtime , Debug and Profiling ),I develop new solution and enhancement for customer problems. I quickly adapt to new software/hardware environment and also help other getting ramp up . I have also know how of Simulation , Synthesis. Prototyping and Verification flows. Specialties: C/C++, Verilog , System Verilog , Perl, Python

Experience

21 yrs 7 mos
Total Experience
4 yrs 4 mos
Average Tenure
5 yrs 2 mos
Current Experience

Cadence design systems

Software Architect

Apr 2021 – Present · 5 yrs 2 mos · Noida

SystemVerilogEDA

Synopsys inc

Senior Staff Software Engineer

Nov 2013 – Apr 2021 · 7 yrs 5 mos

SystemVerilogEDA

Mentor graphics

LMTS

Jul 2006 – Nov 2013 · 7 yrs 4 mos

  • Bug fixes and Feature Enhancement in Behavioral synthesis compiler used in Transaction Based Emulation in C++ . Language Constructs enhancements using Analyzer Apis .
SystemVerilogEDABehavioral synthesis

Interra systems

MTS

Jan 2005 – Jan 2006 · 1 yr

  • Development of Master and Slave VIP for I2C in Open Vera . RTL wrapper creation for the memory models . Testbench Creation using C APIs provided .
EDAASIC

Freescale semiconductor

Design Engineer

May 2004 – Apr 2005 · 11 mos

  • Unit Level and System Level Design Verification of the DDR -SDRAM controller in three networking SOC. Automation of the testbench in OpenVera.
ASICSoC

Education

Banaras Hindu University

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 2000 – Jan 2004

Indian Institute of Technology (Banaras Hindu University), Varanasi

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 2000 – Jan 2004

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Rajendra Kumar - Software Engineer | Stackforce