Dec 2023 – Oct 2024 · 10 mos · India · On-site

• · Played leadership role on last two projects projects with technical guidance of 7 team members and actively involved in project planning, resource management, and interface between other groups.
• · 7+ years of experience as an ASIC/IP Design & Development Engineer with experience on IP and SOC.
• · Experience as an ASIC/IP and SOC Design & Development Engineer with experience on IP.
• · Worked on SOC level static checks like LINT and CDC
• · Exposure to complete ASIC Cycle viz Design, RTL Coding, Unit level Verification, Clock Domain Crossing analysis, Lint analysis, synthesis.
• · Follow industry standard practices, learn, and apply new technologies quickly where applicable.
• · Managed fresh teams to understand the ASIC cycle.
• · Good exposure on Spyglass CDC, Design Compiler for Synthesis.
• · Experience on Integration and design works for different blocks.
• · Good knowledge on design and worked coding for a block for FiFO
• · Experience in timing issues debugging and improved the SDC
• · Good Knowledge on UPF and worked on low power Synthesis.
• · Good understating of interface protocols AMBA & communication protocol Pcie.

Jan 2021 – Aug 2023 · 2 yrs 7 mos · India · Remote

Jun 2019 – Dec 2020 · 1 yr 6 mos · India · On-site

Jul 2016 – Jun 2019 · 2 yrs 11 mos