Achanta Hari — Product Engineer
1. Digital Design Engineer with 7+ years of experience in ASIC, FPGA, RTL, DSP, and high-speed interface design. Currently working on ASIC/SerDes related digital design and DSP RTL development with exposure to high-speed communication systems and hardware debugging. Strong expertise in: • RTL Design – Verilog, SystemVerilog, VHDL • DSP Hardware Implementation – FFT/IFFT, Filters, CORDIC, • ASIC Design Flow – STA, CDC, Low Power Design Techniques • Protocols – AXI4, SPI, I2C, UART • FPGA Platforms – Xilinx Zynq 7000, Ultrascale • Tools – Verdi, Vivado, ModelSim, MATLAB
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC and FPGA technologies.
Location: Amalāpuram, Andhra Pradesh, India
Experience: 8 yrs 5 mos
Skills
- Asic Design
- Rtl Design
- Fpga Design
Career Highlights
- 7+ years in ASIC and FPGA design.
- Expertise in RTL and DSP hardware implementation.
- Proficient in high-speed communication systems.
Work Experience
Synopsys Inc
ASIC Digital Design, Staff Engineer (1 yr 10 mos)
eInfochips (An Arrow Company)
Senior Engineer (11 mos)
Capgemini Engineering
Senior Professional engineer (1 yr)
Unistring Tech Solutions Pvt. Ltd. (UTS)
FPGA DESIGN & RTL Application engineer (4 yrs 8 mos)
Education
Master of Technology - MTech at BITS Pilani Work Integrated Learning Programmes
Bachelor of Technology - BTech at Velagapudi Ramakrishna Siddhartha Engineering College
