Tigran Danielyan — Software Engineer
Analog Design Engineer at Synopsys with a telecommunications and radio physics foundation, specializing in DDR I/O timing characterization and static timing analysis. I generate and analyze timing reports, debug timing issues, and drive setup/hold closure through targeted fixes across corners and constraints. I support and improve STA flows, perform multi-corner analysis, and contribute to block-level sign-off for AMS designs by resolving violations and strengthening timing robustness.
Stackforce AI infers this person is a Telecommunications and Analog Design Engineering specialist with a focus on network performance and timing analysis.
Location: Yerevan, Yerevan, Armenia
Experience: 3 yrs 1 mo
Skills
- Analog Design Engineering
- Static Timing Analysis
- Telecommunications Engineering
- Network Performance Management
Career Highlights
- Expert in DDR I/O timing characterization.
- Proficient in static timing analysis and debugging.
- Strong background in telecommunications engineering.
Work Experience
Synopsys Inc
Analog Design Engineer (1 yr 5 mos)
Viva
Transmission Engineer (1 yr 8 mos)
Team Telecom Armenia
Telecommunications Engineer (2 mos)
Education
Master's degree at Yerevan State University
Bachelor's degree at Yerevan State University