Srilatha SSP

Product Manager

Bengaluru, Karnataka, India10 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in SRAM layout design for advanced semiconductor processes.
Strong background in VLSI and embedded systems.
Proven experience in physical verification of complex designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and layout design.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)

Other Skills

SRAM layout designTSMC 65nmTSI 180nmphysical verificationVerilogVHDL

Experience

10 yrs 4 mos

Total Experience

9 yrs 4 mos

Average Tenure

8 yrs 5 mos

Current Experience

Synopsys inc

2 roles

A&MS staff engineer

Promoted

Dec 2020 – Present · 5 yrs 6 mos · Bengaluru, Karnataka, India · On-site

A & MS Design Engineer -2

Jan 2018 – Dec 2020 · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Sankalp semiconductor

Design Engineer

Feb 2016 – Present · 10 yrs 4 mos · Banglore

SRAM layout design in TSMC 65nm, TSI 180nm
Layouts of important building blocks like array, IO block, leaf cells of control block, pre decoder
Responsible for the physical verification of blocks

SRAM layout designTSMC 65nmTSI 180nmphysical verificationVery-Large-Scale Integration (VLSI)

Education

BITS Pilani

Master of Technology - MTech — VLSI and embedded system

Jun 2017 – Jun 2019

SJMIT

Jan 2011 – Jan 2015

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