Sopaan Shukla

Software Engineer

Bengaluru, Karnataka, India5 yrs 3 mos experience

Key Highlights

Expert in Automatic Test Pattern Generation and Design For Test.
Proven experience in Analog Flows and Application Development.
Strong background in Shell Scripting and GUI development.

Stackforce AI infers this person is a skilled EDA engineer with expertise in DFT and automation.

Contact

Skills

Core Skills

Automatic Test Pattern GenerationDesign For TestAnalog FlowsApplication DevelopmentAutomating Quality Assessment

Other Skills

EDAIC TestSilicon Lifecycle SolutionsATPGEDTSSNTessentShell ScriptingGUI developmentKRAKEN frameworkPyQt5 LibrarySchematic SuiteLayout SuiteModgenSpectre

About

ATPG –  Pattern Generation & Simulation (Siemens Tessent Visualizer; Spyglass Verdi) o Resolved DRC issues in tracing like E14, T3, R14, T5, R1 etc. o Resolving P1 in sourcing and calling PDLs. o Writing Flat model and creating README to load flat model. o Pattern generation and simulation debug.  PLDRC to check for sanity checks of DFT design (Spyglass from Synopsys) Completed PLDRC on two successfully taped out projects. Resolved Clock_11,26, Async_07, Conn_01,02,09,10 rules. Wrote my own rules to check existence of ports for pre-MBIST insertion.  IDDQ o Listing out pins responsible to put a chip in ON and OFF state to get Q current o Creating OFF sequence to shut down the whole chip in an order to avoid X-propagation. o Debugged JDR programming issues by scrutinizing test setup. o PA simulations o Bringing up all core merge session (EDTs inclusive for all cores) ST -> Software development - 1. Python - Development of a tool based on Kraken Framework (written in python, based on MVC architecture ). 2. PyQt5 Library (USER INTERFACE designing) 3. GIT (version control). 4. Crontab. 5. Used OOPS extensively. Linux side - 1. Comfortable with command line interface 2. Shell scripting (Writing scripts to automate validation)

Experience

5 yrs 3 mos

Total Experience

Average Tenure

Current Experience

Qualcomm

2 roles

Sr. DFT Engineer

Promoted

Nov 2023 – Present · 2 yrs 7 mos

Automatic Test Pattern GenerationEDAIC TestSilicon Lifecycle SolutionsATPGDesign For Test+3

DFT Engineer

Aug 2021 – Sep 2025 · 4 yrs 1 mo

Cadence design systems

Internship Trainee

Jul 2021 – Aug 2021 · 1 mo · Bengaluru, Karnataka, India

Stmicroelectronics

Internship Trainee

Aug 2020 – Jun 2021 · 10 mos · Noida, Uttar Pradesh, India

I worked here mainly in 3 domains:
1. Analog Flows -
Worked as Co - Author in publication of "Early Layout Area & PLS estimation by Designers".
Our research got selected VLSID 2021 & DAC 2021.
While working on this paper, I had hands on most of the analog Flow (Schematic -> Floorplanning -> PnR -> Layout -> DRC, LVS cleaning -> PLS-> Area Estimation).
The tools used by me were Schematic suite, Layout Suite, Modgen, Spectre from Cadence & Calibre from Mentor, Animate preview from Pulsic
2. Application Development : -
Working in GUI development of various tools using KRAKEN framework and PyQt5 Library in python.
Learning SKILL for automations in Cadence environment.
Learning Tcl/Tk for automations.
Learnt how to share data from GIT server.
3. Automating Quality Assessment :-
Wrote Shell scripts to automate the flow of validating a tool.
Made a CSH wrapper to run a script which took various arguments as inputs
Extensive use of Shell Scripting using Emacs & gvim as editors

Analog FlowsApplication DevelopmentAutomating Quality AssessmentShell ScriptingGUI developmentKRAKEN framework+1

Bharat electronics limited

SMT Line Engineer

Jul 2018 – Dec 2018 · 5 mos · panchkula

I had two roles :
1. SMT line engineer : -
Handled Automatic Optical Inspection Machine in SMT Line independently
Handling machines involves in PCB production (SMT Line stages)
2. Assistant to Secretary of Machinery Committee : -
Handled Procurement Processes & Documentation
Consulting various stake holders, Supplying Minutes of meeting, Keeping Record of Tenders and other Documents
Hands on work involved in PROCUREMENT procedure.