Lalit Gangwar — Software Engineer

I work as a DFT Engineer supporting SoC test readiness from early planning through implementation and verification. My role includes test plan generation, where I define DFT scope, coverage expectations, and validation strategy for scan, MBIST, BISR, and boundary scan. I am involved in SSN and IP-level testing, ensuring correct DFT behavior and smooth integration at the SoC level. Using Tessent, I handle DFT setup and ATPG pattern generation, and I debug RTL and gate-level simulations using VCS and Xcelium to resolve miscompares and runtime issues. I also use SpyGlass for RTL quality checks and DFT rule analysis to catch structural issues early. My work includes managing test collateral such as STIL, WGL, PDL, BSDL, and ICL, along with supporting IJTAG (IEEE 1687) and JTAG (IEEE 1149.1) access flows. To improve efficiency, I develop Tcl and Perl automation for regression execution and analysis. I take ownership of assigned DFT deliverables and work closely with design and verification teams to drive stable and manufacturable test solutions. #DFT #DFTEngineer #DesignForTest #VLSI #ASIC #Semiconductor #ATPG #ScanInsertion #MBIST #IJTAG #EDA

Stackforce AI infers this person is a Semiconductor Testing Specialist with strong DFT and automation expertise.

Experience: 3 yrs 2 mos