Dipak Patil — DevOps Engineer
Around 5 Years of industry experience in SoC Verification, Development of Verification IP/Coverage driven Constrained Random Verification. Exposure on various ON-CHIP bus architectures: AMBA 5 (CHI- Coherent Hub Interconnect), ACE, AXI. Experience in development of Verification IP in System Verilog (AMBA4 and AMBA5). Testbench development using ARM CMN600. Proficient in HVLs( System Verilog), Methodologies (UVM/OVM/),Cache concepts. Hands on experience on all leading simulators Synopsys-VCS, IUS. Exposure in RCS (Revision Control Systems) tools like Perforce.
Stackforce AI infers this person is a VLSI Verification Engineer with strong expertise in ASIC design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 3 mos
Skills
- Asic
- Vlsi
Career Highlights
- 5 years of experience in SoC Verification.
- Expertise in AMBA bus architectures.
- Proficient in System Verilog and UVM methodologies.
Work Experience
Synopsys Inc
R&D Sr. Staff (2 yrs 3 mos)
R&D Staff (2 mos)
R&D Sr II (2 yrs 1 mo)
R&D Sr I (2 yrs 9 mos)
R&D II (1 yr 11 mos)
CAE (1 yr 5 mos)
Emulex
Asic Verification Intern (10 mos)
Education
MTech VLSI at National Institute of Technology Karnataka
Bachelor of Engineering (B.E.) at Savitribai Phule Pune University
