AVINASH MISHRA — Software Engineer
Gold Medalist at MNNIT Allahabad in M.Tech from Microelectronics and VLSI Design, AIR 714 in GATE 2018. A dedicated and diligent learner, currently working as a Sr. Physical Design Engineer at Renesas Electronics with a proven track record. My responsibilities include synthesis, block level PnR (Floorplanning, Power-Planning, placement optimizations, CTS and routing), custom layout designing of Analog Mixed Signal Circuits, physical verifications (DRC, LVS, ERC, Antenna checks), extractions, spectre/AMS simulations and EMIR checks using voltus-fi for various Automotive IPs. Worked on various projects based on deep submicron FINFET and Fully Depleted SOI technologies like 5nm, 16nm, 22nm, 28nm and 40nm. Knowledge of Static Timing concepts, its pessimistic calculations due to on-chip variations, clock uncertainty, CPPR and CRPR. Understanding of timing & design constraints, aocv & pocv. Experience in Genus, Innovus Stylus, Cadence Virtuoso, Cadence Spectre/Xcelium simulator, Mentor Calibre and TCL/Shell/Python scripting.
Stackforce AI infers this person is a Physical Design Engineer specializing in Automotive and Analog Mixed Signal technologies.
Location: Noida, Uttar Pradesh, India
Experience: 5 yrs 10 mos
Skills
- Physical Design Engineering
- Analog Mixed Signal Design
Career Highlights
- Gold Medalist in M.Tech from MNNIT Allahabad
- Expertise in Physical Design for Automotive IPs
- Proven track record in Analog Mixed Signal Circuits
Work Experience
Renesas Electronics
Sr Physical Design Engineer (11 mos)
NXP Semiconductors
Senior Design Engineer (3 yrs 3 mos)
Design Engineer (1 yr 8 mos)
Technical Student Intern (11 mos)
Education
Master of Technology - MTech at Motilal Nehru National Institute Of Technology
Bachelor of Technology at FEROZE GANDHI INSTITUTE OF ENGG AND TECHNOLOGY , RAEBARELI
Engineering Aspirant Student at CSRL
Intermediate at Jawahar Navodaya Vidyalaya - JNV