Dec 2021 – Present · 4 yrs 6 mos · Sri Lanka

• Unified Compile : FDCP, CONDXOPT, OOB, Multiple Driven, Memory, Loops, etc. - zFmCheck simulation, VCS, Simon Synthesis, C/C++ codebases, System Verilog/VHDL testcases, Customer designs, tcl, bom, etc. ZeBu, Protocompiler, VC Static, Lint flows & enhancements.
• ZeBu and HAPS (HAV) R&D Engineering Operations, Automation, Analytics Projects :
• IWYU (Include What You Use) : R&D Codebase optimization and cleanup of 1000s of C/C++ files - Improvements in Compile Time, Memory, etc. by faster & fewer recompiles, dependency cutting, etc.
• SCBTR (Sandbox Client Build TAT Reduction) : Purple poster-women and SDG purple poster published. EILC submitted.
• Coverage : LCOV dashboard, auto-reporting, visualization, etc.
• Scalability : ZeBu sub-stage log data extraction and visualization
• Chime development for ZeBu & PC R&D check-ins, Chime API (ZS6, EP2, etc.), ACA dashboard, etc.
• Auto-JIRA : Fully automated daily JIRA Create/Validate/Close/Re-open for SCBTR high TAT codebase files and nightly regression failures (L0, L0 Prime & L1 Prime). Global teammates simply run my scripts I authoured, via crons, without manual intervention.
• Benchmark automation for R&D and PV : CTBM, Critical BM, QMS (Quality Management System)
• R&D Regression Automation and Maintenance, Venus Triangulation, Must pass list, machine load changes, etc.
• vgbuild debugging - opt/debug/arm build, Clang, PCI, sandbox, etc.
• Dashboards, auto-reporting (emails, cronjobs, etc.)
• ...
• Knowledge sharing globally (US/South Korea/India/Sri Lanka/...)
• I am one of the first ZeBu R&D engineers in Sri Lanka and joined R&D on invitation.

Feb 2018 – Dec 2021 · 3 yrs 10 mos · Sri Lanka

• Automation, ZeBu, HAPS, Synplify, UCPC, VCS, Simon, zFast, zFmCheck, VC Formal, VC Static, Design Compiler, Fusion Compiler, VS, Spyglass, Formality, HAWK, Verdi, DVE, nWave, nCompare, zCui, Perforce, Probe, vgp4checkin, RTLDB, RhinoDB, Edif, UVM, etc.
• I am the primary developer of the automated multi-product, multi-hardware, multi-stream/release/version, multi-flow unit_SYNTHESIS common VGT regression framework and I successfully migrated 80,000+ unit testcases in less than 1 year. Common VGT is very powerful & results in the demise of PV. Hence for ethical reasons I moved away from the project after I joined R&D.
• Projects:
• zFmCheck for ZeBu (gencase, etc.), UCPC (scm2srs, etc.) and VC Formal
• SmartFV (Formality, VC Formal, UCPC)
• Native/Non-Native Force-Release for ZeBu, PC & UCPC
• Real Number Modelling (RNM), Gate delay, AMS, Floating Point Optimization, Transport delay pointer, ...
• XMR (Cross Module Reference), $hdl_xmr, XMR with variable select
• Memory initialization via readmem.dump
• RTL Name Validation Check (VCS, ZeBu)
• Simon Option Processing
• Simon High Level Loop Transformation
• Scalene
• DPI, zDPI
• SimXL
• zNetgen Elimination
• Power Estimation (SAIF,...)
• ZEMI3, ZEMI4
• QoR (Quality of Results) automation, LabView
• Benchmark and Regression (unit_ZEBU, unit_SYNTHESIS, unit_ZEMI3, unit_SVI, unit_VS, etc.) convergence and automation: Backout analysis, failure triage, URT, CRM, Star, JIRA, ts.verify, regrun, vgt, makefile, csh, tcl, diffs, causes, exclude list, Probe, ...
• Regression to BM auto-converter (Converts unit testcases to BM and auto-validates within few days)
• Auto unit testcase generators: Given HDL and dependency files/commands (e.g. utf file/options), create complete testcase and give steps to validate auto-generated testcase/s by running and then check-in to Perforce.
• Randomized unit testcase generators
• Wrote SolveNet Articles
• ...
• I am a founding engineer of ZeBu and Protocompiler in Sri Lanka and have extensively trained & mentored many others over the years.