mahesh v

Product Manager

Bengaluru, Karnataka, India15 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC and VLSI design.
  • Strong background in RTL design and verification.
  • Proficient in multiple hardware description languages.
Stackforce AI infers this person is a VLSI and ASIC design expert with strong capabilities in hardware verification.

Contact

LinkedIn

Skills

Core Skills

AsicVlsi

Other Skills

VerilogCSystemVerilogVHDLPerlFunctional VerificationRTL DesignDebuggingStatic Timing AnalysisEDAFPGAModelSimSoCLinuxEmbedded Systems

Experience

15 yrs 7 mos
Total Experience
8 yrs 8 mos
Average Tenure
15 yrs 7 mos
Current Experience

Synopsys inc

5 roles

Mgr R&D

Promoted

Jan 2024 – Present · 2 yrs 5 mos

VerilogASICVLSICSystemVerilogVHDL+16

R&D Engineer, Sr II

Feb 2021 – Dec 2023 · 2 yrs 10 mos

R&D Engineer, Sr I

Promoted

Jun 2018 – Jan 2021 · 2 yrs 7 mos

R&D Engineer II

Dec 2016 – May 2018 · 1 yr 5 mos

VG Consultant

Aug 2010 – Dec 2016 · 6 yrs 4 mos

Kacper technologies pvt ltd

Member and Technical Staff

Aug 2010 – May 2012 · 1 yr 9 mos

Education

Visvesvaraya Technological University

M.Tech — VLSI & Embedded System Design

Jan 2007 – Jan 2009

RGMCET

B.TECH — ECE

Jan 2003 – Jan 2007

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