Udhayakumar Jayavelu

Software Engineer

Bengaluru, Karnataka, India17 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

15+ years in ASIC Front-End Design Verification
Expertise in LPDDR memory controller verification
Contributed to major VLSI companies

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in memory controller and IP verification.

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Skills

Core Skills

Memory Controller VerificationSystem VerilogSoc VerificationTest Scenario DevelopmentUpf VerificationTest Plan DevelopmentRtl Regression DebugIp VerificationTest Case Development

Other Skills

LPDDR5LPDDR4LPDDR2System Verilog-UVMC++UPFPower ArtistAXINVMePCIeAHBLPDDR4/4xSpecmanAHCISCSIe

About

I have 15+ years of work experience in ASIC Front-End Design Verification of IPs, Sub-systems, SoC with contributions spanning across major VLSI companies like Intel, Samsung, Qualcomm. During my career, I have contributed to Intel Server Interconnect IP verification, Intel Secondary Storage Device Sub-System verification, Samsung Secondary Storage Device Host Controller IP verification, Qualcomm Low Power DDR SoC verification, Qualcomm Low Power DDR Generations 2/4/5 Memory Controller Core IP Verification, Qualcomm Low Power DDR Debug IP Sub-system verification using System Verilog based UVM methodology.

Experience

17 yrs 5 mos

Total Experience

4 yrs 4 mos

Average Tenure

5 yrs

Current Experience

Qualcomm

Staff Engineer

Jun 2021 – Present · 5 yrs · India · On-site

Responsible for LPDDR2/LPDDR4/LPDDR5 Memory Controller Core IP verification with activities involving test plan development to coverage closure.
Responsible for technically leading/delivering LPDDR Memory Controller Core IP verification with team of size 8
Responsbile for LPDDR Debug IP/Sub-System verification with team of size 4

LPDDR5LPDDR4LPDDR2Memory Controller VerificationSystem Verilog

Smartplay technologies - an aricent company

5 roles

Technical Lead

Feb 2021 – May 2021 · 3 mos · On-site

Responsible for Intel Optane-based SSD SoC Verification
Develop test scenarios covering End2End datapath from PCIe to Media using SV-UVM
Develop error scenarios along with Interrupt Service Routine in C++
Support to create the FPGA identified design issues & root cause the exact design issue
Modify the existing test in SV-UVM/C++ to optimize the code & maximize design testing
Tools : Synopsys VCS, DVE
Languages : System Verilog-UVM, C++, UPF, Power Artist
Protocols : AXI, NVMe, PCIe

System Verilog-UVMC++UPFPower ArtistAXINVMe+3

Technical Lead

Dec 2018 – Jan 2021 · 2 yrs 1 mo · On-site

Responsible for Intel Optane-based SSD SoC Verification
Develop test scenarios covering End2End datapath from PCIe to Media using SV-UVM
Develop error scenarios along with Interrupt Service Routine in C++
Support to create the FPGA identified design issues & root cause the exact design issue
Modify the existing test in SV-UVM/C++ to optimize the code & maximize design testing
Tools : Synopsys VCS, DVE
Languages : System Verilog-UVM, C++, UPF, Power Artist
Protocols : AXI, NVMe, PCIe

System Verilog-UVMC++UPFAXINVMePCIe+2

Technical Lead

Mar 2018 – Nov 2018 · 8 mos · On-site

Responsible for Intel Optane-based SSD SoC Verification
Develop test scenarios covering End2End datapath from PCIe to Media using SV-UVM
Develop error scenarios along with Interrupt Service Routine in C++
Support to create the FPGA identified design issues & root cause the exact design issue
Modify the existing test in SV-UVM/C++ to optimize the code & maximize design testing
Tools : Synopsys VCS, DVE
Languages : System Verilog-UVM, C++, UPF
Protocols : AXI, NVMe, PCIe

System Verilog-UVMC++UPFAXINVMePCIe+2

Technical Lead

Oct 2017 – Mar 2018 · 5 mos · On-site

Responsible for Intel Sub-system UPF Verification.
Develop the Power sequence & incorporated into the existing SV-UVM testbench environment.
Define the test plan, functional coverage points & develop the test scenarios.
Identify UPF related bugs and fixed it with the help of designers.
Achieved complete functional coverage for all retainable registers with random values
Tools : Synopsys VCS, DVE
Languages : System Verilog-UVM, UPF
Protocols : AXI

System Verilog-UVMUPFAXIUPF VerificationTest Plan Development

Technical Lead

Nov 2015 – Aug 2017 · 1 yr 9 mos · Bengaluru Area, India

Responsible for Qualcomm LPDDR4/4x Memory Controllers SoC Verification
Understand the architecture changes & existing SV-UVM/C++ environment
Redefine the test plan, test scenarios based on architecture changes
RTL regression debugs & achieve 100% toggle coverage
Gate-level Simulation (Timing/Nontiming) verification
UPF-aware RTL/Non-timing Netlist verification
Vector Environment bring-up, pattern generation & Silicon debug with ATE engineers
Tools : Synopsys VCS, Verdi
Languages : System Verilog-UVM, C++, UPF
Protocols : AXI, AHB, LPDDR4/4x

System Verilog-UVMC++UPFAXIAHBLPDDR4/4x+2

Samsung electronics

2 roles

Lead Engineer

Promoted

Mar 2012 – Nov 2015 · 3 yrs 8 mos · Bengaluru Area, India

Responsible for IP verification of AHCI, NVMe, SCSIe based Samsung SSD
Understand the design architecture
Define/develop the test plan, test bench architecture, test scenarios (including error scenarios)
Regression failure debugs
Achieve 100% functional coverage & code coverage (with waivers)
Tools : Cadence ncsim/irun, Simvision
Languages : System Verilog-UVM, Specman
Protocols : AXI, AHCI, NVMe, SCSIe, PCIe

System Verilog-UVMSpecmanAXIAHCINVMeSCSIe+3

Senior Software Engineer

Jul 2011 – Mar 2012 · 8 mos · Bengaluru Area, India

Responsible for IP verification of Samsung proprietary 4x1 AXI Master arbiter logic. Define the test plan, develop the test bench architecture, test scenarios including Error scenarios & regression debug.
Tools : Cadence ncsim/irun, Simvision
Languages : System Verilog-UVM, Specman
Protocols : AXI, AHCI, NVMe, SCSIe, PCIe

System Verilog-UVMSpecmanAXIAHCINVMeSCSIe+3