Nitisha Sabbavarapu

Product Engineer

India10 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in hardware security and low-power design.
  • Led initiatives in power management and feature verification.
  • Experience in biomedical machine learning algorithm acceleration.
Stackforce AI infers this person is a Hardware Engineer specializing in low-power design and security for semiconductor industries.

Contact

Skills

Core Skills

Hardware SecurityDebug IpSoc ArchitectureLow PowerHardware Acceleration

Other Skills

Power ManagementSecurity featuresMachine learningApplication-Specific Integrated Circuits (ASIC)Python (Programming Language)Low-power Design

About

Hardware engineer experienced in IP and SoC design and verification, graduated from National Institute of Technology Calicut in VLSI and have a strong interest in building efficient and reliable hardware systems. I’m looking for opportunities where I can do meaningful work, grow technically, and be part of teams that value expertise.

Experience

10 yrs 10 mos
Total Experience
8 yrs 5 mos
Average Tenure
2 yrs 5 mos
Current Experience

Amd

MTS - Silicon Design Engineer

Jan 2024Present · 2 yrs 5 mos

  • Hardware Security Lead
  • Working on security for client, S3 and dgpu projects.
Hardware SecurityDebug IPPower Management

Intel corporation

2 roles

Silicon Architect

Jan 2023Jan 2024 · 1 yr

  • Enabling Intel based debug architecture on SoCs.
Debug IPSoC architecture

Pre-Silicon Engineer

Aug 2015Jan 2023 · 7 yrs 5 mos

  • Debug IPs - Into low power, security and functional features.
  • Led all power management activities and implementation of various low-power IP features. Managed feature verification from initial architecture bring up to coverage closure, while also driving initiatives and improvements. Handled complex post-silicon debugs, from root cause to workarounds. Key contributor in enhancing the quality of IP architecture documentation.
  • Worked on profiling and hardware acceleration of multiple biomedical machine learning algorithms. Presented a portion of this work as an MTech course project at NITC' 2015.
Low powerDebug IPPower ManagementSecurity features

Education

National Institute of Technology Calicut

Master of Technology - MTech — Microelectronics and VLSI Design

Jawaharlal Nehru Technological University

Bachelor of Technology - BTech — Electronics and Communications Engineering

St. Joseph's Girls' High School

High School

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