Christiano Scarpati Alvarenga

Software Engineer

São Paulo, São Paulo, Brazil7 yrs 3 mos experience

Key Highlights

Expert in low latency trading systems development.
Strong background in embedded systems and network programming.
Proficient in C++ and Verilog for hardware design.

Stackforce AI infers this person is a Fintech and EDA specialist with expertise in low latency systems and embedded programming.

Contact

Skills

Core Skills

C++Rtl CodingHardware EmulationCompiler ConstructionFpgaLow Latency TradingNetwork ProgrammingEmbedded Systems

Other Skills

VerilogProfiling ToolsEDADebuggingSoftware TroubleshootingLogic DesignCLionSoftware DevelopmentLogic SynthesisTCLDigital ElectronicsVery-Large-Scale Integration (VLSI)Product ValidationGNU MakeGraph Theory

About

I am passionate about computer science and engineering. 💻 Bachelor’s degree in Computer Engineering (Universidade Federal do Espírito Santo) 🔤 C, C++ 98, 11, 14 ⏏️ Digital Circuits and FPGA (Verilog, VHDL, Timing constraints, Clock Domain Crossing) 🤖 VLSI concepts (Simulation, Timing, Cells, Characterization, DFT) 🐧Unix/Linux programming (sockets, epoll/select, threading) 🔀 Multithreading 📚 STL / Boost 🌐 Socket programming (TCP, UDP) 🛠️ Profiling / tuning 🐞 Debugging 🔗 Version control systems: Git, Perforce 🧱 Build systems: Make, CMake 🌱 Computer science foundations: Algorithms and Data Structures, Operating Systems, Digital Systems, Computer Organization/Architecture

Experience

7 yrs 3 mos

Total Experience

1 yr 9 mos

Average Tenure

Current Experience

Qubika

Senior Embedded Engineer I

May 2026 – Present · 1 mo · Remote

Silvaco inc

Software Engineer

Aug 2024 – May 2026 · 1 yr 9 mos · Porto Alegre, Rio Grande do Sul, Brazil · Remote

Synopsys inc

Software Engineer

Jul 2023 – May 2024 · 10 mos · Santiago, Santiago Metropolitan Region, Chile · On-site

Maintenance, Debugging and Profiling of a RTL-to-GDSII Compiler.
Maintenance of tests.
Close contact with PV to implement improvements.
Execution Excellence Award.

C++VerilogProfiling ToolsEDADebuggingRTL Coding+9

Cadence design systems

Software Engineer

Jan 2022 – Jun 2023 · 1 yr 5 mos · Belo Horizonte, Minas Gerais, Brazil · On-site

Contribution to development of new features of Palladium Emulation.
Key contribution to the STIL Compiler development (STIL-to-SystemVerilog).
Zodiaco tool: new LSF automation tool Development using LSF C API and Boost Graph.

GNU MakeGraph TheoryC++Hardware EmulationData StructuresPerforce+16

Startup

Hardware Engineer

Jul 2021 – Dec 2021 · 5 mos · Sorocaba, São Paulo, Brazil · On-site

FPGA Low Latency Trading.
Digital system in Verilog.
Vivado IDE.
C Software to Communicate with the FPGA Board.

RTL DesignNetwork ProgrammingC++Field-Programmable Gate Arrays (FPGA)VerilogLow Latency Trading+8

Onesoft tecnologia s.a.

Software Engineer

Sep 2018 – Dec 2021 · 3 yrs 3 mos · São Paulo, Brazil · On-site

High Frequency Trading Industry.
Maintenance, debugging, profiling and creation of Trading software.
SBE and FAST decoders.
B3 Market Data.
Unix Programming.
Low Latency Systems.
Multithreading.

POSIXFIXNetwork ProgrammingC++Socket ProgrammingGit+14

Núcleo de processamento de dados (npd)

Software Engineer

Feb 2014 – Sep 2014 · 7 mos · Vitória, Espírito Santo, Brazil · On-site

Development of a Linux Embedded system which reads information of sensors and supply it to network using SNMP protocol.
Reverse Engineering of a SMS No-break with RS-485 Serial Protocol.
Implementation of protocol Serial Protocol.
MSP430 Microcontroller development using C language and IAR Workbench.

SensorsSNMPRaspberry PiPython (Programming Language)C (Programming Language)RS-485+4