Tuan Nguyen

Software Engineer

Ho Chi Minh City, Vietnam5 yrs 8 mos experience

Highly Stable

Key Highlights

Led successful TSMC 2nm TCAM compiler project.
Expert in semiconductor design and advanced process technologies.
Proven track record in driving innovation and efficiency.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in embedded memory technologies.

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Skills

Core Skills

Embedded Memory DesignSemiconductor Design

Other Skills

TCAM compilerproject planningtask allocationtechnical reviewscompiler characterizationdesign margin analysisverificationProcess Entitlementdevice characteristicslayout-dependent effectssimulation vectorsmeasurement flowsPi modelling techniquefunctional verificationcomprehensive characterization

About

Experienced Embedded Memory Design Engineer with over 5 years of expertise in semiconductor design and development. Deep knowledge of advancded process technologies and full design flow, from concept to tape-out. Adept at cross-functional collaboration, working closely with modelling, layout and verification teams to deliver high-quality products on schedule. Good communication skills and proven track record of driving innovation and efficiency in design environments.

Experience

5 yrs 8 mos

Total Experience

5 yrs 6 mos

Average Tenure

1 mo

Current Experience

Qualcomm

Engineer, Senior

May 2026 – Present · 1 mo · Ho Chi Minh City Metropolitan Area · On-site

Synopsys inc

4 roles

R&D Engineering, Staff Engineer

Promoted

Feb 2024 – Apr 2026 · 2 yrs 2 mos · Ho Chi Minh City, Vietnam

Project Leader of TSMC 2nm TCAM compiler for a junior engineering team, achieving first-time tape-out success in the market. Directed project planning, task allocation, and technical reviews to ensure timely and high-quality deliverables. Demonstrated leadership skills in communication, problem-solving, and decision-making to guide the team through complex challenges in cutting-edge technology.
Conducted compiler characterization for TCAM (3nm/2nm) to evaluate performance and power across multiple architectures and workloads. Debugged and corrected mismatches between the characterization netlist and FullRC netlist.
Reviewed design margin analysis and verification for TCAM (3nm/2nm) to ensure circuit robustness across process, voltage, and temperature (PVT) variations. Optimized margins without compromising performance, achieving improvements with minimal design iterations.
Performed comprehensive characterization of TCAM, SRAM bitcells, including analysis of Read/Write/Compare ability, static noise margin (SNM), and leakage currents.
Performed Process Entitlement for a new technologies including TSMC (2nm), Intel (18A), Samsung (4nm/2nm) systematically. Analyze device characteristics, ring oscillator, layout-dependent effects (LDE), metal wire parasitics. Define guideline for layout engineers, propose design strategies, signal routing and power routing plan.

TCAM compilerproject planningtask allocationtechnical reviewscompiler characterizationdesign margin analysis+6

R&D Engineer, Sr I

Jan 2024 – Feb 2024 · 1 mo · Ho Chi Minh City, Vietnam

Conducted compiler characterization for MRAM (22nm/16nm) to evaluate performance and power across multiple architectures and workloads. Developing simulation vectors and measurement flows from scratch, studying and implementing new methodologies for the team.
Built Read/Write critical path for MRAM (22nm/16nm) using Pi modelling technique.

compiler characterizationsimulation vectorsmeasurement flowsPi modelling techniqueEmbedded Memory DesignSemiconductor Design

R&D Engineer, II

Promoted

Apr 2022 – Jan 2024 · 1 yr 9 mos · Ho Chi Minh City, Vietnam

Performed design margin analysis and verification for MRAM (22nm/16nm).
Performed Functional Verification for MRAM (22nm/16nm), reviewed testbench, identified and resolved violations.
Performed comprehensive characterization of MRAM, and ReRAM bitcells, including analysis of Read/Write/Compare ability and leakage currents.
Performed Process Entitlement for a new technologies including TSMC (22nm/16nm), Samsung (4nm).
Developed a tool to collect IR drop data across the entire compiler database, reducing review time from 1~2 weeks to just 4~6 hours.

design margin analysisfunctional verificationcomprehensive characterizationProcess EntitlementIR drop data collectionEmbedded Memory Design+1

R&D Engineer, I

Aug 2020 – Apr 2022 · 1 yr 8 mos · Ho Chi Minh City, Vietnam

Performed Process Entitlement for a new technologies including TSMC (5nm/3nm).
Performed detailed analysis of sense amplifier (SA).
Developed a script package designed to comprehensively analyze device characteristics systematically, including saturation and linear current, threshold voltage, and layout-dependent effects.

Process Entitlementsense amplifier analysisscript package developmentEmbedded Memory DesignSemiconductor Design

Renesas electronics

DFT Trainee

Apr 2020 – Jun 2020 · 2 mos · Ho Chi Minh City, Vietnam

Assisted in Design-for-Test (DFT) implementation for digital IC designs, including scan insertion and ATPG pattern generation.
Gained knowledge of DFT concepts, Scan/ATPG, Fault coverage analysis, EDA tools, Digital design fundamentals, Problem-solving.

Design-for-Test implementationscan insertionATPG pattern generation