Gande Sai Vineeth

Software Engineer

Hyderabad, Telangana, India6 yrs 2 mos experience

Key Highlights

Expert in Analog & Mixed Signal IC Layout Design.
Hands-on experience with cutting-edge Fin-FET & Planar technologies.
Proficient in industry-standard EDA tools for layout verification.

Stackforce AI infers this person is a Semiconductor Layout Engineer with expertise in advanced IC design technologies.

Contact

Skills

Core Skills

Layout Design EngineerAnalog Layout

Other Skills

Cadence Virtuoso Layout EditorFloor PlansSynopsys IC CompilerIntelTsmcLow-power DesignSemiconductor EngineeringAnalog SemiconductorsAnalog CircuitsSemiconductor PhysicsTeamworkHspiceCadence Schematic CaptureVery-Large-Scale Integration (VLSI)Design Rule Checking (DRC)

About

Experienced Analog & Mixed signal IC Layout design engineer ● Hands on experience in Fin-FET & Planar technologies which includes TSMC (2nm, 5nm, 7nm, 12nm, 16nm & 28nm), Intel 3nm. ● In depth familiarity in layout design for sub blocks of SERDES Phy i.e., RX, TX, PLL ● Expertise in physical verification (DRC, LVS), ● Electrical Checks (ERC), DFM checks (PM, Missing vias, Density checks) ● Knowledge of layout effects i.e., Matching, Reliability, Antenna, Proximity effects, Spacing effects, Stress effects. ● Aware of layout techniques to mitigate ESD, latch-up & overcoming max density and min density challenges. ● Knowledge of design for reliability i.e., EM, IR ● Knowledge of signal integrity issues i.e., clock/data routes, differential routing, shielding ● Exposure to industry standard EDA tools like Cadence Virtuoso & Synopsys Custom Compiler for Schematic and Layout Edit. ● Calibre & ICV for Layout Verification like DRC, LVS, and StarRC for PEX (Parasitic) Extraction

Experience

6 yrs 2 mos

Total Experience

1 yr 9 mos

Average Tenure

11 mos

Current Experience

Micron technology

Senior Engineer, HBM Layout

Jul 2025 – Present · 11 mos · Hyderabad, Telangana, India · On-site

(Cadence Virtuoso)
Worked on TSMC 12nm (HBM 4)
Worked on 8-channel sub blocks.
Presently working on TSMC 3nm (HBM 5)
Working on TSV to PHY routings. Optimising by using methodology flows.

Cadence Virtuoso Layout EditorAnalog LayoutLayout Design Engineer

Synopsys inc

Layout Design, Sr Engineer

Dec 2023 – Jul 2025 · 1 yr 7 mos · Hyderabad, Telangana, India · On-site

(Custom Compiler)
Managed layout design for Intel 3nm technology, focusing on Tx and Rx sub-blocks, ensuring compliance with Intel foundry processes.
Executed layout design for TSMC 5nm, emphasising PCIE7 Cm_ana sub-blocks, achieving significant improvements in LVS and DRC.
Conducted static IR drop analysis and EM fixes, enhancing overall design integrity and performance.
Executed layout design for TSMC 2nm, emphasising PCIE7 RX_DLL & TX_DLL.

Floor PlansLayout Design EngineerAnalog Layout

Cyient

AMS Layout Engineer

Apr 2022 – Oct 2023 · 1 yr 6 mos · Hyderabad, Telangana, India · On-site

(Custom Compiler)
Engaged in 7nm technology (TSMC). Focused on SERDES blocks including:
CTLE (Continuous Time Linear Equaliser)
CDR (Clock Data Recovery)
DFE (Decision Feedback Equaliser)
Tia (Trans-impedance Amplifier)
Handled Floor-planning, top level DRC, density checks, and Antenna fixes.

Analog LayoutSynopsys IC CompilerLayout Design Engineer

Risetime semiconductors

Layout Engineer

Jan 2020 – Mar 2022 · 2 yrs 2 mos · Hyderabad, Telangana, India

(Cadence virtuoso & Custom compiler)
Worked on phase frequency detector cell creation using TSMC 16nm in Cadence Virtuoso.
Worked on standard cell creation using 28 & 45 nm TSMC in Cadence Virtuoso.

Floor PlansCadence Virtuoso Layout EditorLayout Design EngineerAnalog Layout