Tarun Goyal

Software Engineer

Sunnyvale, California, United States6 yrs 5 mos experience
Most Likely To SwitchAI Enabled

Key Highlights

  • Reduced customer runtime by ~92% with AI model.
  • Directed delivery of workflows with 10+ stakeholders.
  • Established AI/ML as a viable direction for product line.
Stackforce AI infers this person is a Semiconductor R&D Engineer with expertise in AI/ML and product innovation.

Contact

Skills

Core Skills

Research And Development (r&d)Engineering ManagementArtificial Intelligence (ai)C++Algorithms

Other Skills

FPGA prototypingCollaborative R&DProduct R&DEngineering ConsultingData StructuresTensorFlowEngineering LeadershipDebuggingElectrical EngineeringElectronicsRoboticsComputer-Aided Design (CAD)Analytical SkillsSoftware Development Life Cycle (SDLC)Object-Oriented Programming (OOP)

About

I build the software that builds the chips powering modern technology. For 9 years in deep semiconductor R&D at Synopsys, I’ve worked on ProtoCompiler and HAPS — the software and FPGA-based prototyping systems that let semiconductor teams validate complex chip designs and bring up software well before silicon is ready. I’m hands-on in C++ and data structures, and over time my work has grown from feature development into product innovation, customer-facing problem solving, and cross-team technical leadership. A few things I’ve worked on that I’m proud of: • Built an AI-based area estimation model that cut customer runtime by ~92% — a 2-hour workflow reduced to roughly 10 minutes. • Directed delivery of critical memory-mapping workflows, coordinating 10+ stakeholders across multiple teams to meet client milestones. • Deployed deep neural networks into legacy EDA workflows to predict route delays, helping establish AI/ML as a viable direction for the product line. I think of myself as a hybrid — an engineer comfortable both debugging a tough convergence issue under deadline and scoping what’s worth building in the first place. That second question is why I’m pursuing an iMBA at the University of Illinois (UIUC ’28): to build real fluency in strategy, finance, and product management as I move toward product leadership for AI-driven EDA. Outside work: high-altitude trekking, and reading about geopolitical history and global economics. Happy to connect with people working across AI, semiconductors, and product.

Experience

6 yrs 5 mos
Total Experience
3 yrs 2 mos
Average Tenure
6 yrs
Current Experience

Synopsys inc

6 roles

Senior Staff R&D Engineer

Promoted

May 2026Present · 1 mo

  • Lead technical execution and mentorship within the ProtoCompiler/HAPS R&D organization, partnering across R&D, product validation, and field teams to align roadmap priorities with strategic-account needs. Introduced structured, cross-geography code reviews and a mentorship program that accelerated ramp-up for junior engineers and improved delivery reliability.
Research and Development (R&D)FPGA prototypingCollaborative R&DProduct R&DEngineering ConsultingEngineering Management

Staff R&D engineer

Promoted

Feb 2024May 2026 · 2 yrs 3 mos

  • Led product-innovation work on ProtoCompiler/HAPS spanning AI/ML and developer productivity.
  • Led development of an AI-based area estimation model that reduced customer runtime by ~92% (2 hours → ~10 minutes), improving customer satisfaction and supporting renewals.
  • Directed delivery of critical memory-mapping workflows, coordinating 10+ stakeholders across multiple teams to meet client milestones.

Senior R&D engineer II

Jan 2024Feb 2024 · 1 mo

Senior R&D Engineer I

Promoted

Dec 2021Jan 2024 · 2 yrs 1 mo

  • Served as a primary technical contact on customer escalations for ProtoCompiler/HAPS, diagnosing complex prototyping bring-up and convergence issues under tight deadlines.
  • Partnered with geographically distributed R&D and field teams to triage defects and prioritize features against customer and competitive pressure.

R&D Engineer II

Apr 2019Dec 2021 · 2 yrs 8 mos

  • Joined the ProtoCompiler/HAPS R&D team as a core developer following the VC-Static internship.
  • Improved Quality of Results (~1%) by optimizing core algorithms — a key competitive differentiator in the FPGA prototyping market.
  • Built and deployed deep neural networks (TensorFlow) into legacy workflows to predict route delays, establishing a precedent for AI/ML adoption in the product line.
  • Developed new tool features and improved compilation performance for FPGA-based prototyping.

Intern

Sep 2017Apr 2019 · 1 yr 7 mos

  • Member of the VC-Static Common Component R&D team.
  • Developed new tool features and improved tool performance.
  • Matched VC-Static command behavior against benchmark tools.
  • Resolved bugs and Valgrind/memory-leak issues, and raised LCOV coverage to strengthen regression quality.
  • Designed multithreading algorithms that optimized design-query performance.

Quark software inc.

Trainee

Jan 2017Jun 2017 · 5 mos · Chandigarh, Chandigarh, India

  • Member of the QuarkXPress R&D team.
  • Localized QuarkXPress 2017 for multi-language support and automated the localization process.
  • Added High-DPI support and ported the codebase from Xcode 7.3 to 8.3.
  • Re-architected the code so other teams could make changes without R&D involvement.
  • Resolved bugs across the product.

Education

University of Illinois Urbana-Champaign

Master of Business Administration - MBA

Mar 2026Present

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — software systems

Jan 2020Jan 2022

UIET Panjab University

Bachelor of Engineering — Electronics & Communication Engineering

Jan 2013Jan 2017

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