C

Christo K Thomas

Product Engineer

Worcester, Massachusetts, United States13 yrs 6 mos experience
AI ML PractitionerAI Enabled

Key Highlights

  • Ph.D. in signal processing for wireless communications.
  • Best Student Paper Award at IEEE SPS conference SPAWC2018.
  • Industry experience in ASIC design for modem technologies.
Stackforce AI infers this person is a Telecommunications Engineer with expertise in signal processing and integrated circuit design.

Contact

Skills

Core Skills

Research CollaborationScholarly ResearchAiWireless CommunicationsSemantic CommunicationIntegrated Circuit DesignDigital Signal Processing

Other Skills

Viterbi DecoderMaximum Likelihood DetectorSystem VerilogLint AnalysisCDC AnalysisDeep LearningVHDLCEmbedded SystemsMatlabC++OVMRTL designFunctional VerificationLTE

About

I hold a Ph.D. degree from EURECOM, France, with my research focused on signal processing algorithms for next-generation wireless communications. Specifically, during PhD, I have dedicated my studies to hybrid and digital beamforming techniques for Massive MIMO, asymptotic analysis of Massive MIMO spectral efficiency using random matrix theory, and the application of approximate Bayesian inference techniques. My interest in approximate Bayesian inference extends to methods like belief propagation, variational Bayesian inference, and expectation propagation. In addition to my work on signal processing algorithms, I have also explored tensor signal processing, with a specific focus on massive MIMO channel estimation in multidimensional domains such as delay, Doppler, and spatial domains. I am intrigued by the potential of deep learning in nonlinear signal processing and have begun acquiring skills in Python and TensorFlow to explore this area further. My dedication and contributions were recognized with a Best Student Paper Award at the IEEE SPS conference SPAWC2018. Prior to pursuing my Ph.D., I gained valuable industry experience in the communication chip sector, working at Broadcom Communications and Intel Corporation in Bangalore, India, for a combined duration of five years. During my time in the industry, I primarily focused on ASIC design for 4G LTE modem and G.FAST broadband modem technologies. I developed proficiency in programming languages such as Verilog, VHDL, SystemC, and System Verilog. I acquired a comprehensive understanding of modem SOC development, encompassing RTL design, verification, and design quality analysis, including lint, CDC, power, and area analysis.

Experience

13 yrs 6 mos
Total Experience
2 yrs 1 mo
Average Tenure
10 mos
Current Experience

Worcester polytechnic institute

Assistant Professor

Aug 2025Present · 10 mos · Worcester, MA · On-site

Virginia tech bradley department of electrical & computer engineering

Postdoctoral Researcher

Jun 2022Jul 2025 · 3 yrs 1 mo · Arlington, Virginia, United States

  • AI for wireless, Semantic Communication
Research CollaborationScholarly Research

Qualcomm

Staff Engineer

Nov 2020Jun 2022 · 1 yr 7 mos · Finland

Eurecom

Doctoral Researcher

Jun 2017Oct 2020 · 3 yrs 4 mos · Sophia Antipolis, Biot, France

  • Interests: Signal Processing for Wireless Communications, Information Theory and Approximate Bayesian Inference Methods, Machine Learning.

Intel corporation

IP Logic Design Engineer

Nov 2015Apr 2017 · 1 yr 5 mos

Lantiq

Design Engineer

Nov 2014Oct 2015 · 11 mos · Bengaluru Area, India

Broadcom inc.

Engineer Staff 2, IC Design

Jul 2012Aug 2014 · 2 yrs 1 mo · Bangalore

  • My responsibilities include...
  • 1.Was part of the design team for 4G modem. Worked on the
  • design and verification of Viterbi Decoder and Maximum Likelihood
  • Detector blocks in the receiver datapath of the modem.
  • 2.
  • For the design, I had worked on the Lint and CDC analysis of
  • the above blocks and the entire cellular modem core blocks. Analysis
  • and experiments were done to improve the area of the design.
  • 3.
  • Got an opportunity to evaluate the possibility of synthesizing
  • the RTL for ML detector block directly from the C code (This was done
  • using HLS tool by Forte).
  • 4.
  • I had also worked on the power analysis for the above blocks
  • using power theatre.
  • 5.
  • I was involved in the verification of the viterbi decoder block.
  • The coding was using system Verilog and could get to know and
  • implement using OVM and UVM verification methodologies. The work
  • involved coverpoint coding, regression and coverage closure.
  • 6.
  • Studied LTE Phy Standard and gave presentations to the team.
  • 7.
  • Studied on detail the Control Channel Accelerator (involving
  • vitebi decoder, de-interleaver, de-ratematching) and MLD and gave
  • presentations to the team on these
  • 8.
  • Currently involved in the study of 3G Modules for low cost
  • modem

Indian institute of science

ME Student

Aug 2010Jun 2012 · 1 yr 10 mos · Bangalore

Education

EURECOM

Doctor of Philosophy - PhD

Jun 2017Oct 2020

Indian Institute of Science (IISc)

Master of Engineering - MEng — Telecommunications Engineering

Jan 2010Jan 2012

National Institute of Technology Calicut

B.Tech — Electronics and Communication Engineering

Jan 2006Jan 2010

St Antony's Public School (SAPS), Anakkal, Kanjirappally

Plus Two — Computer Science Batch

Jan 2004Jan 2006

AKJM HSS,Kanjirappally

High School

Jan 1998Jan 2004

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