Shripad Deshpande

CTO

India27 yrs 2 mos experience

Highly StableAI Enabled

Key Highlights

25+ years in hardware design and EDA
Expert in AI-native platforms and SoC architecture
Proven leadership in global engineering teams

Stackforce AI infers this person is a leader in EDA and hardware design, specializing in AI integration and SoC architecture.

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Skills

Core Skills

EdaSocVirtual PrototypingAsipRtl DesignCo-simulationSignal Processing

Other Skills

AI-native hardware designverificationsynthesistoolchain integrationAI integrationSoC Architecturecloud enablementmulti-die modelingSoC architecture explorationPower and Performance optimizationApplication Specific Processor (ASIP)hardware descriptioncompiler generationRTL code synthesisC-HDL Co-simulation

About

Leading R&D at ChipForge, focused on building AI-native platforms that transform how hardware is designed—from intent to silicon. 25+ years of experience across virtual prototyping, SoC architecture, multi-die/chiplet systems, and advanced EDA tools. Proven track record of architecting scalable design platforms, accelerating design cycles, and enabling early, data-driven architecture decisions. Current focus at the intersection of hardware design, EDA, and applied AI—building end-to-end workflows spanning design intent, generation, verification, and synthesis across FPGA and ASIC flows. Experience includes leading global engineering teams, driving product strategy, and delivering architecture exploration and software development tools used for complex SoC and system-level design. Interested in advancing AI-assisted engineering to enable more automated, scalable, and reliable chip design workflows.

Experience

27 yrs 2 mos

Total Experience

9 yrs

Average Tenure

3 mos

Current Experience

Chipforge.ai

Head of R&D - Hardware Design and EDA

Mar 2026 – Present · 3 mos · India

Chipforge: AI-native hardware design & EDA platform
Leading R&D for AI-native hardware design and EDA platforms, shaping the technology strategy and execution roadmap.
Driving end-to-end platform architecture from design intent → HDL → verification → synthesis → deployment (FPGA-first, extensible to ASIC flows)
Building AI-integrated EDA workflows, including natural-language-to-HDL generation, verification loops, and constrained design automation
Leading toolchain integration across simulation, synthesis, and verification backends (open-source and commercial), with focus on reproducibility and automation
Defining scalable system architecture for hybrid, on-premise, sovereign, and cloud deployment environments

EDASoCAI-native hardware designverificationsynthesistoolchain integration

Synopsys inc

5 roles

Sr Director R&D

Promoted

Feb 2024 – Apr 2026 · 2 yrs 2 mos

Provide strategic and technical leadership for Synopsys’ Virtual Prototyping and SoC Architecture Exploration products, overseeing architecture, platform design, cloud enablement, and multi-die modeling. Led global engineering teams developing front-end tools and SystemC/TLM IP models, driving innovation, scaling capabilities, and enabling customers to accelerate design cycles, optimize power-performance, and adopt multi-die/heterogeneous integration.

Virtual PrototypingSoC Architecturecloud enablementmulti-die modelingSoC

Director R&D

Nov 2022 – Mar 2024 · 1 yr 4 mos

Sr R&D Manager

Oct 2016 – May 2021 · 4 yrs 7 mos

Responsible for architecture, design, and implementation of next generation Virtual Prototyping Products. These products are used for SoC architecture exploration, Power and Performance optimization. Leading an engineering team to develop IP models based on SystemC/TLM Modeling at various abstraction levels. Working on enabling integration of several processor models (Tensilica, CEVA, SiFive, Andes, and NXP) in Virtual Prototyping product. Responsible for development and lifecycle management of IP models for multiple product releases.

Virtual PrototypingSoC architecture explorationPower and Performance optimizationSoC

Sr R&D Manager

Promoted

Apr 2010 – Nov 2022 · 12 yrs 7 mos

R&D Manager

Mar 2010 – Sep 2016 · 6 yrs 6 mos

Developed software products for designing Application Specific Processor (ASIP) models. Primary focus area been generate optimized hardware description (VHDL/Verilog) from high level C like language called LISA. Nurtured R&D team in India to build other aspects of the product viz. compiler generation, synthesized RTL code, software debugging etc. Collaborated with local sales team to increase proliferation of Processor Designer tool in various government accounts.

Application Specific Processor (ASIP)hardware descriptioncompiler generationRTL code synthesisASIPRTL design

Coware

Member Consulting Staff

Jan 2004 – Mar 2010 · 6 yrs 2 mos · Noida, Uttar Pradesh, India

Worked on developing C-HDL Co-simulation flow with Mentor (ModelSim) simulator. Contributed in design and implementation of a new (revamped) SPW product, major involvement was on HDS libraries, C-HDL Co-simulation flows and optimized code generation. One of the lead inventors in defining a new methodology for smooth transition of a design from system specification to hardware implementation. Presented this methodology in technical conferences and implemented it in the mainstream product. Developed multiple demonstrators of the flow: WCDMA 3GPP System (Rake receiver) and MPEG4 Codec (DCT).

C-HDL Co-simulationHDS librariesoptimized code generationCo-simulationEDA

Cadence design systems

Senior Member Technical Staff

Apr 1999 – Jan 2004 · 4 yrs 9 mos · Noida, Uttar Pradesh, India

Started career with Cadence as R&D engineer on Signal Processing Workbench (SPW) product which was used for exploration and implementation of complex DSP algorithms. It involved developing C++ based models to generate optimized C and/or synthesizable RTL. These were highly configurable models and were used as building blocks for complex DSP algorithm. Worked on creating links to synthesis tools from Cadence (BuildGates) and Synopsys (Design Compiler) for data-path optimization and low-power synthesis flow. Integrated FPGA synthesis tools (Xilinx and Altera) inside SPW for importing pre-defined FPGA models.

Signal Processing WorkbenchDSP algorithmsC++ modelingSignal ProcessingEDA