Raj Nirmal

Software Engineer

Noida, Uttar Pradesh, India2 yrs experience
Highly Stable

Key Highlights

  • Experienced in Integrated Circuit Design and Digital Logic Design.
  • Proficient in Functional Verification and SystemVerilog.
  • Hands-on experience with Application-Specific Integrated Circuits.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and FPGA development.

Contact

LinkedIn

Skills

Core Skills

Integrated Circuit DesignDigital Logic DesignApplication-specific Integrated Circuits (asic)

Other Skills

Embedded memoriesCircuit DesignRTL DesignFunctional VerificationSystemVerilogFormal VerificationScriptingPython (Programming Language)digital system designRTL VerificationField-Programmable Gate Arrays (FPGA)Mixed-Signal IC DesignSystem on a Chip (SoC)FPGA prototypingvlsi tool

Experience

2 yrs
Total Experience
2 yrs
Average Tenure
2 yrs
Current Experience

Synopsys inc

2 roles

R&D Sr. Engineer

Promoted

May 2026 – Present · 1 mo · On-site

Embedded memoriesCircuit DesignIntegrated Circuit DesignRTL DesignDigital Logic DesignFunctional Verification+17

R&D Engineer

Jun 2024 – May 2026 · 1 yr 11 mos · On-site

Einfochips (an arrow company)

Student Intern

Jun 2023 – Aug 2023 · 2 mos · Ahmedabad, Gujarat, India · Hybrid

Application-Specific Integrated Circuits (ASIC)vlsi tool

Education

Nirma University

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2020 – Jan 2024

Stackforce found 100+ more professionals with Integrated Circuit Design & Digital Logic Design

Explore similar profiles based on matching skills and experience

Arabo Tovmasyan

Arabo Tovmasyan

Senior Member of Technical Staff

at Analog Port AM

Yerevan, Armenia9 yrs 4 mos exp
Vaishnav Achath

Vaishnav Achath

Maintainer

at The Zephyr Project

Bengaluru, India7 yrs 7 mos exp
Embedded SystemsReal-Time Operating Systems (RTOS)Software ArchitectureVirtualizationHypervisor
Akshay Kinake

Akshay Kinake

Staff Signoff Application Engineer

at Synopsys Inc

Bengaluru, India3 yrs 11 mos exp
Full Chip timing signoffSMC 3DIC STATiming ClosurePerformance Optimization
Lovleen Arora

Lovleen Arora

Principal Engineer, NAND SubSystem Device Engineering

at Western Digital

Bengaluru, India9 yrs exp
NAND Flash MemorySystem DesignProduct Development
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Ashutosh Rao

Ashutosh Rao

R&D Engineer

at Synopsys Inc

Bengaluru, India4 yrs 4 mos exp
Static Timing AnalysisCircuit DesignHardware Security
Peter Wohl

Peter Wohl

Fellow

at Synopsys Inc

Williston, United States33 yrs 5 mos exp
ATPGCompressionDFT
Shivaprasad Boddupally

Shivaprasad Boddupally

Analog Design Engineer

at Sophrosyne Semiconductor

Nalgonda, India4 yrs 4 mos exp
Analog Integrated Circuit DesignElectronic Circuit DesignSilicon Validation