Jaeheon Kim — Software Engineer

Master's degree in Electronics Seventeen years of digital and analog circuit design experiences in the electrical engineering industry - Design and Verify OTP and MTP Memory products and testchip - RTL (Verilog/Verilog-AMS) modeling of digital and real number model(Power circuits and OTP/MTP) - Developed expertise in high-speed Memory (DRAM, NAND) and mobile interface (SSTL-DDR3/4, LPDDR2/3/4, mini-LVDS and MIPI) - Design experience with several of analog circuits: LDOs, precision amplifiers, RC oscillators, VCOs, bias circuits, bandgap references, switched-capacitor circuits, ADC/DAC, high-speed receivers/drivers, Serdes, high-speed latches/comparators/level-shifters - Familiar with high-speed I/O signaling and clocking techniques (Data strobe and CLK strobe) - Understanding of CMOS analog / mixed-signal design methodologies and circuit analysis - Excellent ability to design high-speed DRAM circuits (Column/Data Path) - Deep knowledge of display driver ICs and systems (Analog circuits of LCD/OLED driver ICs) - Several experiences of set-up E-fuse in Memory device, OTP IPs in LCD/OLED ICs - Signal integrity and power integrity experiences (PKG/Board/System level) - Exceptional ability of verification in full-chip environment - Hands on in drawing circuit layout and knowledge of ESD requirements - Extremely familiar with essential CAD and simulation tools, such as OrCAD, Virtuoso, ADE, Allegro, Calibre, Hspice, Finesim, Questasim, VCS, Ncsim, etc. - Experience in behavioral modeling of analog blocks (Verilog, IBIS, HSPICE, Matlab, etc.) - Outstanding knowledge of systems and setting up the wafer, PKG and board level test - Good working experience in using test equipments such as spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog and digital designs

Stackforce AI infers this person is a high-speed circuit design expert in the semiconductor industry.

Location: Ottawa, Ontario, Canada

Experience: 19 yrs 1 mo

Skills

High-speed Memory Interface Validation
Nvm Design
Otp/mtp Memory Products
High-speed Interface Design For Dram
Nand And Controller Ic
Analog Circuit And Mobile Interface Design

Career Highlights

Seventeen years of experience in circuit design
Expertise in high-speed memory and mobile interfaces
Proficient in analog and digital circuit verification

Work Experience

Synopsys Inc

Sr Staff Engineer (1 yr 4 mos)

Staff Engineer (1 yr)

Senior Engineer (1 yr 2 mos)

Senior Engineer (5 yrs 7 mos)

SK hynix

Senior Design Engineer (7 yrs)

LG Electronics

Senior Design Engineer (5 yrs 4 mos)

Education

Master's degree at Hanyang University

Bachelor's degree at Hanyang University

Jaeheon Kim

Software Engineer

Ottawa, Ontario, Canada19 yrs 1 mo experience

Highly Stable

Key Highlights

Seventeen years of experience in circuit design
Expertise in high-speed memory and mobile interfaces
Proficient in analog and digital circuit verification

Stackforce AI infers this person is a high-speed circuit design expert in the semiconductor industry.

Contact

Skills

Core Skills

High-speed Memory Interface ValidationNvm DesignOtp/mtp Memory ProductsHigh-speed Interface Design For DramNand And Controller IcAnalog Circuit And Mobile Interface Design

Other Skills

IBISPKGPCB model validationhspice stateyeverilogsystem verilogverilog-amsRTL modelingtestchip developmentESD designFinesimHspiceHigh-speed interface designPre-emphasisDe-emphasis

About

Experience

19 yrs 1 mo

Total Experience

6 yrs 4 mos

Average Tenure

Current Experience

Synopsys inc

4 roles

Sr Staff Engineer

Promoted

Feb 2025 – Present · 1 yr 4 mos · 캐나다 온타리오 오타와 · Hybrid

High speed memory interface validation
IBIS, PKG and PCB model validation using hspice stateye

IBISPKGPCB model validationhspice stateyeHigh-speed memory interface validation

Staff Engineer

Feb 2023 – Feb 2024 · 1 yr

High speed memory interface validation
IBIS, PKG and PCB model validation using hspice stateye

IBISPKGPCB model validationhspice stateyeHigh-speed memory interface validation

Senior Engineer

Dec 2022 – Feb 2024 · 1 yr 2 mos

High speed memory interface validation
IBIS, PKG and PCB model validation using hspice stateye

IBISPKGPCB model validationhspice stateyeHigh-speed memory interface validation

Senior Engineer

May 2017 – Dec 2022 · 5 yrs 7 mos

NVM design (OTP/MTP)
Design, Characterize, Margin, Verify OTP and MTP Memory products
Testchip development for OTP and MTP Memory products
IO ring/ESD design and simulation for testchip
Develop specifications for OTP/MTP designs and testchip
Synopsys Custom Compiler, Finesim, Hspice
RTL (Verilog/ Verilog-AMS) modeling of digital and real number model
Verilog & Verilog real number modeling for Power circuits
Verilog & Verilog-AMS modeling for OTP/MTP circuits
Verify with Verilog & Verilog-AMS testbench
Liberty development with power aware - UDN development
Liberty generation using Nanotime
UPF development
Mentor Questasim & Synopsys VCS

verilogsystem verilogverilog-amsRTL modelingtestchip developmentESD design+4

Sk hynix

Senior Design Engineer

Mar 2010 – Mar 2017 · 7 yrs · Icheon, Gyeonggi-do, Korea

High-speed interface design for DDR3/4 and LPDDR2/3/4 DRAM, NAND and Controller IC
Pre-emphasis/De-emphasis, Slew-rate control for high-speed Transmitter
Serializing scheme for high-speed Transmitter
High-speed/low offset comparator design for interface Calibration scheme
High speed Level-up/down shifter design
Channel simulation and analysis for SI, including PKG/Board/AP load
1-stage/2-stage/3-stage input buffers with CMFB and DFE, CTLE Equalizer for high-speed Receiver
De-skewing scheme for high-speed Receiver
De-serializing scheme and latch for high-speed Receiver
High speed clock tree design & modeling
ESD protection circuit guide for high speed operation
Set-up first E-fuse (kilopass) in DDR3 DRAM
System power integrity modeling & simulation using Finesim, hspice
On chip and PKG/Board capacitance design guide for Power Integrity
Full Chip Function Check using mixed-simulation tools (Finesim)
Produce IBISs for DRAM
PKG ball map estimation for enabling and SI simulation using ADS simulator
Failure analysis using high-speed ATE and oscilloscope

High-speed interface designPre-emphasisDe-emphasisSlew-rate controlChannel simulationPower integrity modeling+3

Lg electronics

Senior Design Engineer

Nov 2004 – Mar 2010 · 5 yrs 4 mos · Seoul, Korea

Analog circuit and Mobile interface circuit design for LCD/OLED Driver ICs
High-speed mini-LVDS Rx design for large scale OLED TV
Mobile Industry Processor Interface (MIPI) HS-RX and LP-TX/RX design for mobile LCD/OLED
Band-gap reference circuit design using chopping for low offset (both cascade/opamp-type)
Rail-to-rail op-amp design for capacitive load
Main bias block (beta-multiplier current bias, two-stage opamp buffer) design
Voltage regulator design for multi-level power generation (low-dropout regulator)
DAC (MOS transistor decoder circuit) design for high resolution
Charge pump circuit design for internal high voltage power without latch-up
Source/Gate MUX (low-to-high level shifter circuit array) design
Gamma generation block design (rail-to-rail op-amp buffer, r-string decoder, MUX, etc.)
Multi-power detection block design
RC-OSC (with internal resistor) and X-tal oscillator circuit design
Several experience of OTP/MTP IPs design in LCD/OLED ICs
Full-chip floorplan (PAD assignment, analog block placement, digital-to-analog signal arrangement, etc.)
Full schematic design for LVS
Full chip verification using mixed-simulation tools (Nanosim, VCS)
Tape-out process follow-up (DRC, LVS, ERC result check, Mask confirm, etc.)
IC wafer test set-up with test engineer (Yokogawa, Advan Test)

Analog circuit designMobile interface circuit designHigh-speed mini-LVDS Rx designBand-gap reference circuit designVoltage regulator designFull-chip verification+1