Satabdi Panda

Software Engineer

Bengaluru, Karnataka, India5 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expertise in PLIB-PCell across multiple technology nodes.
  • Strong foundation in digital electronics and physical design.
  • Proven leadership in layout design and team collaboration.
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on VLSI and layout design.

Contact

LinkedIn

Skills

Other Skills

C (Programming Language)MatlabVHDLVerilogOpen source edaIot audrino basicsTeam LeadershipPublic SpeakingSemiconductorsMosfetsData StructuresInsustrial automationPresentation SkillsBasics of static timing analysisTelemetry

About

A Layout engineer having hands on experience on Intel , Samsung and tsmc technology nodes .Experience in specifically PLIB-PCell with demonstrated history of working on different techno nodes and developing PLIB modules and strong catch on fundamentals.

Experience

5 yrs 8 mos
Total Experience
1 yr 1 mo
Average Tenure
10 mos
Current Experience

Nvidia

Senior Mask Design Engineer

Aug 2025 – Present · 10 mos · Bengaluru, Karnataka, India

Synopsys inc

2 roles

Senior Engineer

Promoted

Dec 2024 – Aug 2025 · 8 mos · Noida, Uttar Pradesh, India

A&MS Layout Engineer I

Apr 2022 – Aug 2025 · 3 yrs 4 mos · Noida, Uttar Pradesh, India

Stmicroelectronics

PDK Device Library Development

Sep 2021 – Apr 2022 · 7 mos · India

Teacheron.com

Student Tutor

Jun 2021 – Sep 2021 · 3 mos

Sevya multimedia

2 roles

Design Engineer

Apr 2021 – Apr 2022 · 1 yr · India

  • PDK and Automation

Project Intern

Jan 2021 – Apr 2021 · 3 mos · India

Silicon institute of technology (sit), bhubaneswar

Teaching Assistant

Jul 2020 – Jan 2021 · 6 mos · Bhubaneshwar, Odisha, India

  • VLSI Design CMOS Circuits labs

Technoready

Trainee

May 2020 – Jul 2020 · 2 mos

  • With vlsiexpert|technoready
  • Outcomes of this course-
  • Basics of logic synthesis
  • Writing timing constraints
  • I/O FILES
  • Design objects
  • Block and soc level synthesis
  • Knowledge on tools
  • Synthesis flow

Vlsi expert private limited

Intern

Feb 2020 – May 2020 · 3 mos

  • It was based on mainly on static timing analysis.
  • What i learnt-
  • Basics of vlsi design flow
  • Why timing in physical design?
  • Standard cells
  • Standard cell files
  • Timing arc
  • Timing checks
  • Delays and delay models
  • Basics of tcl format
  • Cmos inverter
  • Mos characteristics
  • Digital electronics

Defence research and development organisation (drdo)

Summer Intern

Jun 2019 – Jul 2019 · 1 mo · Odisha, India

  • Outcomes-
  • Knowledge about telemetry on board and ground station
  • Missiles testing
  • Knowledge on previous missions
  • Various Drdo dept.
  • Circuit designing
  • Radar
  • Practical knowledge of communication onboard and ground station

Education

Silicon Institute of Technology (SIT), Bhubaneswar

Bachelor of Technology - BTech — Electronics and instrumentation

Jan 2017 – Jan 2021

Stackforce found 100+ more professionals with C (Programming Language) & Matlab

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