Shyama Sasi

Product Engineer

Stockholm, Stockholm County, Sweden4 yrs 8 mos experience

Key Highlights

Expert in FPGA design and verification for aerospace applications.
Proven track record in optimizing large-scale FPGA systems.
Skilled in mentoring and driving project success in agile environments.

Stackforce AI infers this person is a highly skilled FPGA Engineer specializing in aerospace and ASIC prototyping.

Contact

Skills

Core Skills

Fpga DesignEmbedded SystemsFpga PrototypingAsic Design

Other Skills

VHDLPython (Programming Language)C++Digital DesignsVerilogUVMTCLPythonTeam MotivationRISCMicrocontrollersFPGASwedishSystemVerilogUniversal Verification Methodology (UVM)

About

Results-driven FPGA Engineer with 3+ years of experience delivering space-grade and commercial FPGA systems across domains like aerospace, image processing, and ASIC prototyping. At AAC Clyde Space and Synopsys, I’ve worked hands-on with RTL design, verification using SystemVerilog/UVM, and performance optimization for large-scale designs using Vivado, Synplify, and HAPS platforms. I specialize in hardware-software integration, system-level debug, and reusable testbench architecture. I’m passionate about solving complex technical challenges, driving project success in agile environments, and mentoring new engineers. 🔧 Technical stack: Verilog, VHDL, SystemVerilog, UVM, Python, TCL, Vivado, Modelsim, HAPS, DC, Spyglass 🌍 Based in Stockholm | Open to roles in FPGA Design, Verification, Embedded Systems & R&D

Experience

4 yrs 8 mos

Total Experience

Average Tenure

Current Experience

Ericsson

Asic developer

Sep 2025 – Present · 9 mos · Stockholm, Stockholm County, Sweden

Aac clyde space

FPGA Engineer

Aug 2024 – Sep 2025 · 1 yr 1 mo · Uppsala, Uppsala County, Sweden · On-site

Designed and implemented radiation-tolerant FPGA systems using Verilog/VHDL for satellite applications.
Developed modular testbenches, reducing validation time and improving simulation coverage.
Collaborated across firmware, software, and systems teams for embedded integration.
Led debug efforts across FPGA, hardware, and firmware domains.
Created comprehensive technical documentation for traceability and client reporting.

VHDLPython (Programming Language)FPGA DesignEmbedded Systems

Synopsys inc

2 roles

Senior Research And Development Engineer

Promoted

Feb 2023 – May 2024 · 1 yr 3 mos

Worked on Large FPGA Designs and ASIC FPGA Prototypes using Verilog on
Synplify and HAPS.
Used system verilog and uvm testbenches to verify the designs.
Worked on designs for space applications, image processing, hstdm ips etc
Worked with tools like Vivado, Quartus and lattice radiant.
Write and maintain scripts using TCL and Python to automate development
processes.
Developed, debugged, troubleshooted, and maintained HAPS Prototyping and
Synplify software.
Document software design, implementation, and testing procedures.
Worked with dc and spyglass for asic designs and linting.
Regularly solved customer issues, driving customer satisfaction. Participate in
SCRUM and agile setups to enhance team productivity and project efficiency.

C++Digital DesignsFPGA PrototypingASIC Design

Research And Development Engineer

Jul 2021 – Feb 2023 · 1 yr 7 mos

Experience on tools like Vivado,Quartus, Synplify and Protocompiler.
Worked extensively on linux environment with debugging tools like GDB.

C++Team Motivation

Sion semiconductors private limited

FPGA Design Intern

Jun 2020 – Dec 2020 · 6 mos · Bengaluru, Karnataka, India · Remote

Project Management, RTL Coding using Verilog HD, Interface Protocols, SoC Architectures, FPGA Design
IP Development, Testing, Debugging, Benchmarking.
Technologies Used: FPGA, Verilog coding, Platforms like Modelsim and Vivado by Xilinx

RISCMicrocontrollersFPGA Design