Shreeroop Ajaykumar

DevOps Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience

Key Highlights

9+ years in system software architecture
Published inventor with multiple patents
Expert in cache optimization and performance engineering

Stackforce AI infers this person is a Semiconductor Performance Architect with deep expertise in system software and cache optimization.

Contact

Skills

Core Skills

System Cache Software DevelopmentIo Performance AnalysisBenchmark Performance ImprovementArm Cpu Performance Exploration

Other Skills

Embedded SoftwarePerformance AnalysisSystem PerformanceX86Computer ArchitectureMicroarchitectureARM ArchitectureRISC-VC (Programming Language)

About

Staff Engineer with 9+ years of experience in system software architecture and performance engineering across ARM, Qualcomm and AMD. I specialize in cache optimization, CPU & IO performance, and benchmarking—delivering measurable improvements across mobile and server platforms. At Qualcomm, I’ve architected scalable system cache solutions, integrated MPAM for memory partitioning, and developed LLCC performance tooling. My work spans prefetching strategies, cache sizing, and cross-functional collaboration with hardware and firmware teams. Previously at AMD, I led post-silicon validation and filed patents in spinlock optimization and cache injection for multi-die systems. I’ve also contributed to ADAS algorithm development and industrial automation. Proficient in C, Python, ARM assembly, and performance tools like perf, ftrace, and QEMU. Published inventor with patents in synchronization and cache mechanisms. Outside of tech, I’m a self-taught portrait artist with a passion for sketching and oil painting.

Experience

9 yrs 10 mos

Total Experience

1 yr 10 mos

Average Tenure

5 mos

Current Experience

Arm

Staff Engineer (Performance Architecture)

Jan 2026 – Present · 5 mos

Qualcomm

3 roles

Staff Engineer (System Cache SW )

Promoted

Oct 2024 – Feb 2026 · 1 yr 4 mos · Bengaluru, Karnataka, India · On-site

Specialize in developing and optimizing system cache solutions that drive performance and efficiency across modern compute platforms. My current focus spans:
> System Cache Software Development – Architecting robust, scalable cache systems tailored for next-gen workloads.
> MPAM Integration – Enabling fine-grained memory partitioning and access control for enhanced QoS.
> LLCC Perfmon Tooling – Building performance monitoring tools to extract actionable insights from Last-Level Cache Controllers.
> System Cache Sizing Studies – Conducting empirical and analytical evaluations to guide cache provisioning strategies.
> Optimization Techniques – Innovating across prefetching, replacement policies, and warm-up strategies to maximize cache hit rates and minimize latency

Embedded SoftwareSystem Cache Software Development

Sr. Lead Engineer (CPU Performance)

Nov 2021 – Jul 2022 · 8 mos · Bengaluru, Karnataka, India

> Developed sw techniques to improve benchmark (Geekbench, Antutu, SPEC, PCMark etc) performance.
> Implemented various dynamic techniques to improve benchmark scores by exploiting prefetch tunables.
> Worked on PPM (Power Performance Management) features like MPMM (Maximum Power Mitigation Mechanism) and PDP (Performance Defined Power).
> Performance evaluation and validation of Snapdragon Flagship mobile CPU subsystem

Performance AnalysisEmbedded SoftwareBenchmark Performance Improvement

Senior Engineer (CPU Performance)

Mar 2019 – Nov 2021 · 2 yrs 8 mos · Bengaluru, Karnataka, India

> Early performance exploration of ARM CPUs, evaluation of ARM microarchitectural improvements, performance-power trade-offs and drive design of next generation Qualcomm products.
> Analyze bottlenecks/limitations in existing CPU subsystem.
> Analyze new microarchitecture features introduced in ARM ecosystem and explore how they can benefit Qualcomm products.
> Collaborate with Mobile benchmark consortiums and drive benchmark/workload selection that showcases Qualcomm IP strengths.

Performance AnalysisEmbedded SoftwareARM CPU Performance Exploration

Amd

MTS Silicon Design Engineer (Server Performance Group)

Jul 2022 – Oct 2024 · 2 yrs 3 mos · Bengaluru, Karnataka, India

> Worked on IO performance (Network, Storage IO) analysis.
> Worked on performance studies of IOMMU
> Worked on performance evaluation of IOMMU features like DMA Translation, Interrupt Remapping.
> Worked on Spinlock performance studies.
> Proposed patentable ideas for improving spinlock performance.
> Proposed patentable idea for improving energy efficiency of spinlock implementations.
> Proposed patentable idea for improving IPI (Inter Processor Interrupt) performance.

Performance AnalysisSystem PerformanceEmbedded SoftwareX86IO Performance Analysis

Sasken technologies limited

Senior Engineer ( ADAS Algorithm Development )

Oct 2017 – Mar 2019 · 1 yr 5 mos · Bengaluru Area, India

> Algorithm development for camera and RADAR based ADAS applications.
> Developed FCW (Forward collision warning) system using camera ( CNN object detector, object tracking, time to collision estimation using Kalman filtering )
> Developed FCW system using FMCW RADAR ( object detection, tracking, time to collision estimation )

Tata steel

Researcher & Technologist ( Control & Automation )

Aug 2016 – Oct 2017 · 1 yr 2 mos · Jamshedpur, Jharkhand, India

> Design and development of imaging-based quality analysis systems for steel products.
> Improved the detection rate of Rhomboidity measurement system ( camera based system to measure quality of steel bars ) by 50%. This work got selected for the final rounds of TATA Innovista 2017